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Commit fd428c05c863aefb575b12b2a1916b02d5bfa759

Authored by Detlev Zundel
Committed by Wolfgang Denk
1 parent c0c316569f
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mpc5xxx: Remove all references to MGT5100 

We do not support a processor that never reached a real customer.

Signed-off-by: Detlev Zundel <dzu@denx.de>

Showing 59 changed files with 22 additions and 1169 deletions Side-by-side Diff

... ... @@ -80,7 +80,6 @@
80 80  
81 81 Wolfgang Denk <wd@denx.de>
82 82  
83   - IceCube_5100 MGT5100
84 83 IceCube_5200 MPC5200
85 84  
86 85 ARIA MPC5121e
... ... @@ -61,7 +61,6 @@
61 61 EVAL5200 \
62 62 fo300 \
63 63 galaxy5200 \
64   - icecube_5100 \
65 64 icecube_5200 \
66 65 inka4x0 \
67 66 ipek01 \
... ... @@ -76,7 +75,6 @@
76 75 pf5200 \
77 76 PM520 \
78 77 TB5200 \
79   - Total5100 \
80 78 Total5200 \
81 79 Total5200_Rev2 \
82 80 TQM5200 \
1 1 #
2   -# (C) Copyright 2000-2009
  2 +# (C) Copyright 2000-2010
3 3 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 #
5 5 # See file CREDITS for list of people who contributed to this
... ... @@ -548,8 +548,7 @@
548 548 icecube_5200_LOWBOOT08_config \
549 549 icecube_5200_DDR_config \
550 550 icecube_5200_DDR_LOWBOOT_config \
551   -icecube_5200_DDR_LOWBOOT08_config \
552   -icecube_5100_config: unconfig
  551 +icecube_5200_DDR_LOWBOOT08_config: unconfig
553 552 @mkdir -p $(obj)include
554 553 @mkdir -p $(obj)board/icecube
555 554 @[ -z "$(findstring LOWBOOT_,$@)" ] || \
... ... @@ -568,14 +567,6 @@
568 567 { echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \
569 568 $(XECHO) "... DDR memory revision" ; \
570 569 }
571   - @[ -z "$(findstring 5200,$@)" ] || \
572   - { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \
573   - $(XECHO) "... with MPC5200 processor" ; \
574   - }
575   - @[ -z "$(findstring 5100,$@)" ] || \
576   - { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \
577   - $(XECHO) "... with MGT5100 processor" ; \
578   - }
579 570 @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
580 571  
581 572 jupiter_config: unconfig
... ... @@ -594,7 +585,6 @@
594 585 @mkdir -p $(obj)board/icecube
595 586 @ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h
596 587 @ $(XECHO) "... DDR memory revision"
597   - @ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h
598 588 @ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h
599 589 @[ -z "$(findstring _PM_,$@)" ] || \
600 590 { echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \
... ... @@ -604,7 +594,6 @@
604 594 { echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
605 595 $(XECHO) "... with LOWBOOT configuration" ; \
606 596 }
607   - @ $(XECHO) "... with MPC5200B processor"
608 597 @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
609 598  
610 599 mcc200_config \
611 600  
... ... @@ -728,21 +717,12 @@
728 717 @ echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
729 718 @$(MKCONFIG) -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
730 719  
731   -Total5100_config \
732 720 Total5200_config \
733 721 Total5200_lowboot_config \
734 722 Total5200_Rev2_config \
735 723 Total5200_Rev2_lowboot_config: unconfig
736 724 @mkdir -p $(obj)include
737 725 @mkdir -p $(obj)board/total5200
738   - @[ -z "$(findstring 5100,$@)" ] || \
739   - { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \
740   - $(XECHO) "... with MGT5100 processor" ; \
741   - }
742   - @[ -z "$(findstring 5200,$@)" ] || \
743   - { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \
744   - $(XECHO) "... with MPC5200 processor" ; \
745   - }
746 726 @[ -n "$(findstring Rev,$@)" ] || \
747 727 { echo "#define CONFIG_TOTAL5200_REV 1" >>$(obj)include/config.h ; \
748 728 $(XECHO) "... revision 1 board" ; \
board/bc3450/bc3450.c
Diff comments   View file @ fd428c0
... ... @@ -104,7 +104,6 @@
104 104 * is something else than 0x00000000.
105 105 */
106 106  
107   -#if defined(CONFIG_MPC5200)
108 107 phys_size_t initdram (int board_type)
109 108 {
110 109 ulong dramsize = 0;
... ... @@ -204,57 +203,6 @@
204 203 return dramsize;
205 204 }
206 205  
207   -#elif defined(CONFIG_MGT5100)
208   -
209   -phys_size_t initdram (int board_type)
210   -{
211   - ulong dramsize = 0;
212   -#ifndef CONFIG_SYS_RAMBOOT
213   - ulong test1, test2;
214   -
215   - /* setup and enable SDRAM chip selects */
216   - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
217   - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */
218   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
219   - __asm__ volatile ("sync");
220   -
221   - /* setup config registers */
222   - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
223   - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
224   -
225   - /* address select register */
226   - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
227   - __asm__ volatile ("sync");
228   -
229   - /* find RAM size */
230   - sdram_start(0);
231   - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
232   - sdram_start(1);
233   - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
234   - if (test1 > test2) {
235   - sdram_start(0);
236   - dramsize = test1;
237   - } else {
238   - dramsize = test2;
239   - }
240   -
241   - /* set SDRAM end address according to size */
242   - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
243   -
244   -#else /* CONFIG_SYS_RAMBOOT */
245   -
246   - /* Retrieve amount of SDRAM available */
247   - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
248   -
249   -#endif /* CONFIG_SYS_RAMBOOT */
250   -
251   - return dramsize;
252   -}
253   -
254   -#else
255   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
256   -#endif
257   -
258 206 int checkboard (void)
259 207 {
260 208 #if defined (CONFIG_TQM5200)
... ... @@ -276,10 +224,6 @@
276 224 * Note that CS_BOOT cannot be cleared when
277 225 * executing in flash.
278 226 */
279   -#if defined(CONFIG_MGT5100)
280   - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
281   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
282   -#endif
283 227 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
284 228 }
285 229  
board/bc3450/mt48lc16m16a2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 /* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
... ... @@ -33,16 +32,4 @@
33 32 /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
34 33 #define SDRAM_CONFIG2 0x8AD70000
35 34 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
36   -
37   -#elif defined(CONFIG_MGT5100)
38   -/* Settings for XLB = 66 MHz */
39   -#define SDRAM_MODE 0x008D0000
40   -#define SDRAM_CONTROL 0x504F0000
41   -#define SDRAM_CONFIG1 0xC2222600
42   -#define SDRAM_CONFIG2 0x88B70004
43   -#define SDRAM_ADDRSEL 0x02000000
44   -
45   -#else
46   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
47   -#endif
... ... @@ -81,7 +81,6 @@
81 81 * is something else than 0x00000000.
82 82 */
83 83  
84   -#if defined(CONFIG_MPC5200)
85 84 phys_size_t initdram (int board_type)
86 85 {
87 86 ulong dramsize = 0;
... ... @@ -182,57 +181,6 @@
182 181  
183 182 return dramsize + dramsize2;
184 183 }
185   -
186   -#elif defined(CONFIG_MGT5100)
187   -
188   -phys_size_t initdram (int board_type)
189   -{
190   - ulong dramsize = 0;
191   -#ifndef CONFIG_SYS_RAMBOOT
192   - ulong test1, test2;
193   -
194   - /* setup and enable SDRAM chip selects */
195   - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
196   - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
197   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
198   - __asm__ volatile ("sync");
199   -
200   - /* setup config registers */
201   - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
202   - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
203   -
204   - /* address select register */
205   - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
206   - __asm__ volatile ("sync");
207   -
208   - /* find RAM size */
209   - sdram_start(0);
210   - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
211   - sdram_start(1);
212   - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
213   - if (test1 > test2) {
214   - sdram_start(0);
215   - dramsize = test1;
216   - } else {
217   - dramsize = test2;
218   - }
219   -
220   - /* set SDRAM end address according to size */
221   - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
222   -
223   -#else /* CONFIG_SYS_RAMBOOT */
224   -
225   - /* Retrieve amount of SDRAM available */
226   - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
227   -
228   -#endif /* CONFIG_SYS_RAMBOOT */
229   -
230   - return dramsize;
231   -}
232   -
233   -#else
234   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
235   -#endif
236 184  
237 185 int checkboard (void)
238 186 {
board/canmb/mt48lc16m32s2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,22 +23,9 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 #define SDRAM_CONTROL 0x504F0000
30 29 #define SDRAM_CONFIG1 0xD2322800
31 30 #define SDRAM_CONFIG2 0x8AD70000
32   -
33   -#elif defined(CONFIG_MGT5100)
34   -/* Settings for XLB = 66 MHz */
35   -#define SDRAM_MODE 0x008D0000
36   -#define SDRAM_CONTROL 0x504F0000
37   -#define SDRAM_CONFIG1 0xC2222600
38   -#define SDRAM_CONFIG2 0x88B70004
39   -#define SDRAM_ADDRSEL 0x02000000
40   -
41   -#else
42   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
43   -#endif
board/esd/cpci5200/mt46v16m16-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 1 /* is DDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x018D0000
29 28 #define SDRAM_EMODE 0x40090000
... ... @@ -31,8 +30,4 @@
31 30 #define SDRAM_CONFIG1 0x73722930
32 31 #define SDRAM_CONFIG2 0x47770000
33 32 #define SDRAM_TAPDELAY 0x10000000
34   -
35   -#else
36   -#error CONFIG_MPC5200 not defined
37   -#endif
board/esd/mecp5200/mt46v16m16-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 1 /* is DDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x018D0000
29 28 #define SDRAM_EMODE 0x40090000
... ... @@ -31,8 +30,4 @@
31 30 #define SDRAM_CONFIG1 0x73722930
32 31 #define SDRAM_CONFIG2 0x47770000
33 32 #define SDRAM_TAPDELAY 0x10000000
34   -
35   -#else
36   -#error CONFIG_MPC5200 not defined
37   -#endif
board/esd/pf5200/mt46v16m16-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 1 /* is DDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x018D0000
29 28 #define SDRAM_EMODE 0x40090000
... ... @@ -31,8 +30,4 @@
31 30 #define SDRAM_CONFIG1 0x73722930
32 31 #define SDRAM_CONFIG2 0x47770000
33 32 #define SDRAM_TAPDELAY 0x10000000
34   -
35   -#else
36   -#error CONFIG_MPC5200 not defined
37   -#endif
board/icecube/icecube.c
Diff comments   View file @ fd428c0
... ... @@ -134,7 +134,6 @@
134 134 * is something else than 0x00000000.
135 135 */
136 136  
137   -#if defined(CONFIG_MPC5200)
138 137 phys_size_t initdram (int board_type)
139 138 {
140 139 ulong dramsize = 0;
141 140  
142 141  
... ... @@ -258,65 +257,12 @@
258 257 return dramsize + dramsize2;
259 258 }
260 259  
261   -#elif defined(CONFIG_MGT5100)
262   -
263   -phys_size_t initdram (int board_type)
264   -{
265   - ulong dramsize = 0;
266   -#ifndef CONFIG_SYS_RAMBOOT
267   - ulong test1, test2;
268   -
269   - /* setup and enable SDRAM chip selects */
270   - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
271   - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
272   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
273   - __asm__ volatile ("sync");
274   -
275   - /* setup config registers */
276   - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
277   - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
278   -
279   - /* address select register */
280   - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
281   - __asm__ volatile ("sync");
282   -
283   - /* find RAM size */
284   - sdram_start(0);
285   - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
286   - sdram_start(1);
287   - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
288   - if (test1 > test2) {
289   - sdram_start(0);
290   - dramsize = test1;
291   - } else {
292   - dramsize = test2;
293   - }
294   -
295   - /* set SDRAM end address according to size */
296   - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
297   -
298   -#else /* CONFIG_SYS_RAMBOOT */
299   -
300   - /* Retrieve amount of SDRAM available */
301   - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
302   -
303   -#endif /* CONFIG_SYS_RAMBOOT */
304   -
305   - return dramsize;
306   -}
307   -
308   -#else
309   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
310   -#endif
311   -
312 260 int checkboard (void)
313 261 {
314 262 #if defined (CONFIG_LITE5200B)
315 263 puts ("Board: Freescale Lite5200B\n");
316   -#elif defined(CONFIG_MPC5200)
  264 +#else
317 265 puts ("Board: Motorola MPC5200 (IceCube)\n");
318   -#elif defined(CONFIG_MGT5100)
319   - puts ("Board: Motorola MGT5100 (IceCube)\n");
320 266 #endif
321 267 return 0;
322 268 }
... ... @@ -329,10 +275,6 @@
329 275 * Note that CS_BOOT cannot be cleared when
330 276 * executing in flash.
331 277 */
332   -#if defined(CONFIG_MGT5100)
333   - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
334   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
335   -#endif
336 278 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
337 279 }
338 280  
board/icecube/mt46v16m16-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 1 /* is DDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x018D0000
29 28 #define SDRAM_EMODE 0x40090000
... ... @@ -31,8 +30,4 @@
31 30 #define SDRAM_CONFIG1 0x73722930
32 31 #define SDRAM_CONFIG2 0x47770000
33 32 #define SDRAM_TAPDELAY 0x10000000
34   -
35   -#else
36   -#error CONFIG_MPC5200 not defined
37   -#endif
board/icecube/mt46v32m16.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 1 /* is DDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x018D0000
29 28 #define SDRAM_EMODE 0x40090000
... ... @@ -31,8 +30,4 @@
31 30 #define SDRAM_CONFIG1 0x73722930
32 31 #define SDRAM_CONFIG2 0x47770000
33 32 #define SDRAM_TAPDELAY 0x10000000
34   -
35   -#else
36   -#error CONFIG_MPC5200 not defined
37   -#endif
board/icecube/mt48lc16m16a2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,22 +23,9 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 #define SDRAM_CONTROL 0x504F0000
30 29 #define SDRAM_CONFIG1 0xD2322800
31 30 #define SDRAM_CONFIG2 0x8AD70000
32   -
33   -#elif defined(CONFIG_MGT5100)
34   -/* Settings for XLB = 66 MHz */
35   -#define SDRAM_MODE 0x008D0000
36   -#define SDRAM_CONTROL 0x504F0000
37   -#define SDRAM_CONFIG1 0xC2222600
38   -#define SDRAM_CONFIG2 0x88B70004
39   -#define SDRAM_ADDRSEL 0x02000000
40   -
41   -#else
42   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
43   -#endif
board/jupiter/jupiter.c
Diff comments   View file @ fd428c0
... ... @@ -227,10 +227,6 @@
227 227 * Note that CS_BOOT cannot be cleared when
228 228 * executing in flash.
229 229 */
230   -#if defined(CONFIG_MGT5100)
231   - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
232   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
233   -#endif
234 230 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
235 231 }
236 232  
237 233  
... ... @@ -248,10 +244,8 @@
248 244 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
249 245 STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
250 246 }
251   -#if defined(CONFIG_MPC5200)
252 247 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
253 248 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
254   -#endif
255 249 }
256 250  
257 251 int update_flash_size (int flash_size)
board/mcc200/mt46v16m16-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 1 /* is DDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x018D0000
29 28 #define SDRAM_EMODE 0x40090000
... ... @@ -31,8 +30,4 @@
31 30 #define SDRAM_CONFIG1 0x73722930
32 31 #define SDRAM_CONFIG2 0x47770000
33 32 #define SDRAM_TAPDELAY 0x10000000
34   -
35   -#else
36   -#error CONFIG_MPC5200 not defined
37   -#endif
board/mcc200/mt48lc16m16a2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,22 +23,9 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 #define SDRAM_CONTROL 0x504F0000
30 29 #define SDRAM_CONFIG1 0xD2322800
31 30 #define SDRAM_CONFIG2 0x8AD70000
32   -
33   -#elif defined(CONFIG_MGT5100)
34   -/* Settings for XLB = 66 MHz */
35   -#define SDRAM_MODE 0x008D0000
36   -#define SDRAM_CONTROL 0x504F0000
37   -#define SDRAM_CONFIG1 0xC2222600
38   -#define SDRAM_CONFIG2 0x88B70004
39   -#define SDRAM_ADDRSEL 0x02000000
40   -
41   -#else
42   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
43   -#endif
board/mcc200/mt48lc16m32s2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,22 +23,9 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 #define SDRAM_CONTROL 0x504F0000
30 29 #define SDRAM_CONFIG1 0xD2322800
31 30 #define SDRAM_CONFIG2 0x8AD70000
32   -
33   -#elif defined(CONFIG_MGT5100)
34   -/* Settings for XLB = 66 MHz */
35   -#define SDRAM_MODE 0x008D0000
36   -#define SDRAM_CONTROL 0x504F0000
37   -#define SDRAM_CONFIG1 0xC2222600
38   -#define SDRAM_CONFIG2 0x88B70004
39   -#define SDRAM_ADDRSEL 0x02000000
40   -
41   -#else
42   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
43   -#endif
board/munices/mt48lc16m16a2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,22 +23,9 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 #define SDRAM_CONTROL 0x504F0000
30 29 #define SDRAM_CONFIG1 0xD2322800
31 30 #define SDRAM_CONFIG2 0x8AD70000
32   -
33   -#elif defined(CONFIG_MGT5100)
34   -/* Settings for XLB = 66 MHz */
35   -#define SDRAM_MODE 0x008D0000
36   -#define SDRAM_CONTROL 0x504F0000
37   -#define SDRAM_CONFIG1 0xC2222600
38   -#define SDRAM_CONFIG2 0x88B70004
39   -#define SDRAM_ADDRSEL 0x02000000
40   -
41   -#else
42   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
43   -#endif
board/pm520/mt46v16m16-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 1 /* is DDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x018D0000
29 28 #define SDRAM_EMODE 0x40090000
... ... @@ -31,8 +30,4 @@
31 30 #define SDRAM_CONFIG1 0x73722930
32 31 #define SDRAM_CONFIG2 0x47770000
33 32 #define SDRAM_TAPDELAY 0x10000000
34   -
35   -#else
36   -#error CONFIG_MPC5200 not defined
37   -#endif
board/pm520/mt48lc16m16a2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,22 +23,9 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 #define SDRAM_CONTROL 0x504F0000
30 29 #define SDRAM_CONFIG1 0xD2322800
31 30 #define SDRAM_CONFIG2 0x8AD70000
32   -
33   -#elif defined(CONFIG_MGT5100)
34   -/* Settings for XLB = 66 MHz */
35   -#define SDRAM_MODE 0x008D0000
36   -#define SDRAM_CONTROL 0x504F0000
37   -#define SDRAM_CONFIG1 0xC2222600
38   -#define SDRAM_CONFIG2 0x88B70004
39   -#define SDRAM_ADDRSEL 0x02000000
40   -
41   -#else
42   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
43   -#endif
... ... @@ -84,7 +84,6 @@
84 84 * is something else than 0x00000000.
85 85 */
86 86  
87   -#if defined(CONFIG_MPC5200)
88 87 phys_size_t initdram (int board_type)
89 88 {
90 89 ulong dramsize = 0;
91 90  
92 91  
... ... @@ -186,64 +185,9 @@
186 185 return dramsize + dramsize2;
187 186 }
188 187  
189   -#elif defined(CONFIG_MGT5100)
190   -
191   -phys_size_t initdram (int board_type)
192   -{
193   - ulong dramsize = 0;
194   -#ifndef CONFIG_SYS_RAMBOOT
195   - ulong test1, test2;
196   -
197   - /* setup and enable SDRAM chip selects */
198   - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
199   - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
200   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
201   - __asm__ volatile ("sync");
202   -
203   - /* setup config registers */
204   - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
205   - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
206   -
207   - /* address select register */
208   - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
209   - __asm__ volatile ("sync");
210   -
211   - /* find RAM size */
212   - sdram_start(0);
213   - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
214   - sdram_start(1);
215   - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
216   - if (test1 > test2) {
217   - sdram_start(0);
218   - dramsize = test1;
219   - } else {
220   - dramsize = test2;
221   - }
222   -
223   - /* set SDRAM end address according to size */
224   - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
225   -
226   -#else /* CONFIG_SYS_RAMBOOT */
227   -
228   - /* Retrieve amount of SDRAM available */
229   - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
230   -
231   -#endif /* CONFIG_SYS_RAMBOOT */
232   -
233   - return dramsize;
234   -}
235   -
236   -#else
237   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
238   -#endif
239   -
240 188 int checkboard (void)
241 189 {
242   -#if defined(CONFIG_MPC5200)
243 190 puts ("Board: MicroSys PM520 \n");
244   -#elif defined(CONFIG_MGT5100)
245   - puts ("Board: MicroSys PM510 \n");
246   -#endif
247 191 return 0;
248 192 }
249 193  
... ... @@ -255,10 +199,6 @@
255 199 * Note that CS_BOOT cannot be cleared when
256 200 * executing in flash.
257 201 */
258   -#if defined(CONFIG_MGT5100)
259   - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
260   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
261   -#endif
262 202 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
263 203 }
264 204  
board/total5200/mt48lc16m16a2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,22 +23,9 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 #define SDRAM_CONTROL 0x504F0000
30 29 #define SDRAM_CONFIG1 0xD2322800
31 30 #define SDRAM_CONFIG2 0x8AD70000
32   -
33   -#elif defined(CONFIG_MGT5100)
34   -/* Settings for XLB = 66 MHz */
35   -#define SDRAM_MODE 0x008D0000
36   -#define SDRAM_CONTROL 0x504F0000
37   -#define SDRAM_CONFIG1 0xC2222600
38   -#define SDRAM_CONFIG2 0x88B70004
39   -#define SDRAM_ADDRSEL 0x02000000
40   -
41   -#else
42   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
43   -#endif
board/total5200/mt48lc32m16a2-75.h
Diff comments   View file @ fd428c0
... ... @@ -28,14 +28,9 @@
28 28  
29 29 #define SDRAM_DDR 0 /* is SDR */
30 30  
31   -#if defined(CONFIG_MPC5200)
32 31 /* Settings for XLB = 132 MHz */
33 32 #define SDRAM_MODE 0x00CD0000
34 33 #define SDRAM_CONTROL 0x514F0000
35 34 #define SDRAM_CONFIG1 0xD2322800
36 35 #define SDRAM_CONFIG2 0x8AD70000
37   -
38   -#else
39   -#error CONFIG_MPC5200 is not defined
40   -#endif
board/total5200/sdram.c
Diff comments   View file @ fd428c0
... ... @@ -76,7 +76,6 @@
76 76 * is something else than 0x00000000.
77 77 */
78 78  
79   -#if defined(CONFIG_MPC5200)
80 79 long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
81 80 {
82 81 ulong dramsize = 0;
... ... @@ -174,55 +173,4 @@
174 173  
175 174 return dramsize + dramsize2;
176 175 }
177   -
178   -#elif defined(CONFIG_MGT5100)
179   -
180   -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
181   -{
182   - ulong dramsize = 0;
183   -#ifndef CONFIG_SYS_RAMBOOT
184   - ulong test1, test2;
185   -
186   - /* setup and enable SDRAM chip selects */
187   - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
188   - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
189   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
190   - __asm__ volatile ("sync");
191   -
192   - /* setup config registers */
193   - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
194   - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
195   -
196   - /* address select register */
197   - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel;
198   - __asm__ volatile ("sync");
199   -
200   - /* find RAM size */
201   - mpc5xxx_sdram_start(sdram_conf, 0);
202   - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
203   - mpc5xxx_sdram_start(sdram_conf, 1);
204   - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
205   - if (test1 > test2) {
206   - mpc5xxx_sdram_start(sdram_conf, 0);
207   - dramsize = test1;
208   - } else {
209   - dramsize = test2;
210   - }
211   -
212   - /* set SDRAM end address according to size */
213   - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
214   -
215   -#else /* CONFIG_SYS_RAMBOOT */
216   -
217   - /* Retrieve amount of SDRAM available */
218   - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
219   -
220   -#endif /* CONFIG_SYS_RAMBOOT */
221   -
222   - return dramsize;
223   -}
224   -
225   -#else
226   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
227   -#endif
board/total5200/sdram.h
Diff comments   View file @ fd428c0
... ... @@ -28,12 +28,7 @@
28 28 ulong control;
29 29 ulong config1;
30 30 ulong config2;
31   -#if defined(CONFIG_MPC5200)
32 31 ulong tapdelay;
33   -#endif
34   -#if defined(CONFIG_MGT5100)
35   - ulong addrsel;
36   -#endif
37 32 } sdram_conf_t;
38 33  
39 34 long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
board/total5200/total5200.c
Diff comments   View file @ fd428c0
... ... @@ -47,26 +47,17 @@
47 47 sdram_conf.control = SDRAM_CONTROL;
48 48 sdram_conf.config1 = SDRAM_CONFIG1;
49 49 sdram_conf.config2 = SDRAM_CONFIG2;
50   -#if defined(CONFIG_MPC5200)
51 50 sdram_conf.tapdelay = 0;
52   -#endif
53   -#if defined(CONFIG_MGT5100)
54   - sdram_conf.addrsel = SDRAM_ADDRSEL;
55   -#endif
56 51 return mpc5xxx_sdram_init (&sdram_conf);
57 52 }
58 53  
59 54 int checkboard (void)
60 55 {
61   -#if defined(CONFIG_MPC5200)
62 56 #if CONFIG_TOTAL5200_REV==2
63 57 puts ("Board: Total5200 Rev.2 ");
64 58 #else
65 59 puts ("Board: Total5200 ");
66 60 #endif
67   -#elif defined(CONFIG_MGT5100)
68   - puts ("Board: Total5100 ");
69   -#endif
70 61  
71 62 /*
72 63 * Retrieve FPGA Revision.
... ... @@ -85,20 +76,6 @@
85 76 return 0;
86 77 }
87 78  
88   -#if defined(CONFIG_MGT5100)
89   -int board_early_init_r(void)
90   -{
91   - /*
92   - * Now, when we are in RAM, enable CS0
93   - * because CS_BOOT cannot be written.
94   - */
95   - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
96   - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
97   -
98   - return 0;
99   -}
100   -#endif
101   -
102 79 #ifdef CONFIG_PCI
103 80 static struct pci_controller hose;
104 81  
... ... @@ -266,9 +243,7 @@
266 243 void video_get_info_str (int line_number, char *info)
267 244 {
268 245 if (line_number == 1) {
269   -#ifdef CONFIG_MGT5100
270   - strcpy (info, " Total5100");
271   -#elif CONFIG_TOTAL5200_REV==1
  246 +#if CONFIG_TOTAL5200_REV==1
272 247 strcpy (info, " Total5200");
273 248 #elif CONFIG_TOTAL5200_REV==2
274 249 strcpy (info, " Total5200 Rev.2");
board/tqc/tqm5200/mt48lc16m16a2-75.h
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,6 @@
23 23  
24 24 #define SDRAM_DDR 0 /* is SDR */
25 25  
26   -#if defined(CONFIG_MPC5200)
27 26 /* Settings for XLB = 132 MHz */
28 27 #define SDRAM_MODE 0x00CD0000
29 28 /* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
... ... @@ -33,16 +32,4 @@
33 32 /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
34 33 #define SDRAM_CONFIG2 0x8AD70000
35 34 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
36   -
37   -#elif defined(CONFIG_MGT5100)
38   -/* Settings for XLB = 66 MHz */
39   -#define SDRAM_MODE 0x008D0000
40   -#define SDRAM_CONTROL 0x504F0000
41   -#define SDRAM_CONFIG1 0xC2222600
42   -#define SDRAM_CONFIG2 0x88B70004
43   -#define SDRAM_ADDRSEL 0x02000000
44   -
45   -#else
46   -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
47   -#endif
cpu/mpc5xxx/Makefile
Diff comments   View file @ fd428c0
... ... @@ -26,7 +26,7 @@
26 26 LIB = $(obj)lib$(CPU).a
27 27  
28 28 START = start.o
29   -SOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
  29 +SOBJS = io.o firmware_sc_task_bestcomm.impl.o
30 30 COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \
31 31 loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
32 32  
... ... @@ -50,16 +50,10 @@
50 50 {
51 51 ulong clock = gd->cpu_clk;
52 52 char buf[32];
53   -#ifndef CONFIG_MGT5100
54 53 uint svr, pvr;
55   -#endif
56 54  
57 55 puts ("CPU: ");
58 56  
59   -#ifdef CONFIG_MGT5100
60   - puts (CPU_ID_STR);
61   - printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID);
62   -#else
63 57 svr = get_svr();
64 58 pvr = get_pvr();
65 59  
... ... @@ -77,7 +71,6 @@
77 71  
78 72 printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
79 73 PVR_MAJ(pvr), PVR_MIN(pvr));
80   -#endif
81 74 printf (" at %s MHz\n", strmhz (buf, clock));
82 75 return 0;
83 76 }
cpu/mpc5xxx/cpu_init.c
Diff comments   View file @ fd428c0
... ... @@ -53,10 +53,6 @@
53 53 (struct mpc5xxx_gpt *) MPC5XXX_GPT;
54 54 #endif /* CONFIG_WATCHDOG */
55 55 unsigned long addecr = (1 << 25); /* Boot_CS */
56   -
57   -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
58   - addecr |= (1 << 22); /* SDRAM enable */
59   -#endif
60 56 /* Pointer is writable since we allocated a register for it */
61 57 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
62 58  
... ... @@ -136,7 +132,6 @@
136 132 out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
137 133 #endif
138 134  
139   -#if defined(CONFIG_MPC5200)
140 135 addecr |= 1;
141 136 #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
142 137 out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
143 138  
144 139  
... ... @@ -164,14 +159,9 @@
164 159 #if defined(CONFIG_SYS_CS_DEADCYCLE)
165 160 out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
166 161 #endif
167   -#endif /* CONFIG_MPC5200 */
168 162  
169 163 /* Enable chip selects */
170   -#if defined(CONFIG_MGT5100)
171   - out_be32(&mm->addecr, addecr);
172   -#elif defined(CONFIG_MPC5200)
173 164 out_be32(&mm->ipbi_ws_ctrl, addecr);
174   -#endif
175 165 out_be32(&lpb->cs_ctrl, (1 << 24));
176 166  
177 167 /* Setup pin multiplexing */
... ... @@ -179,7 +169,6 @@
179 169 out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
180 170 #endif
181 171  
182   -#if defined(CONFIG_MPC5200)
183 172 /* enable timebase */
184 173 setbits_be32(&xlb->config, (1 << 13));
185 174  
186 175  
187 176  
188 177  
189 178  
190 179  
191 180  
192 181  
193 182  
... ... @@ -187,33 +176,29 @@
187 176 setbits_be32(&xlb->config, (1 << 15));
188 177 out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
189 178  
190   -# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
  179 +#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
191 180 /* Motorola reports IPB should better run at 133 MHz. */
192   -# if defined(CONFIG_MGT5100)
193   - setbits_be32(&mm->addecr, 1);
194   -# elif defined(CONFIG_MPC5200)
195 181 setbits_be32(&mm->ipbi_ws_ctrl, 1);
196   -# endif
197 182 /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
198 183 addecr = in_be32(&cdm->cfg);
199 184 addecr &= ~0x103;
200   -# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
  185 +# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
201 186 /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
202 187 addecr |= 0x01;
203   -# else
  188 +# else
204 189 /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
205 190 addecr |= 0x02;
206   -# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
  191 +# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
207 192 out_be32(&cdm->cfg, addecr);
208   -# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
  193 +#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
209 194 /* Configure the XLB Arbiter */
210 195 out_be32(&xlb->master_pri_enable, 0xff);
211 196 out_be32(&xlb->master_priority, 0x11111111);
212 197  
213   -# if defined(CONFIG_SYS_XLB_PIPELINING)
  198 +#if defined(CONFIG_SYS_XLB_PIPELINING)
214 199 /* Enable piplining */
215 200 clrbits_be32(&xlb->config, (1 << 31));
216   -# endif
  201 +#endif
217 202  
218 203 #if defined(CONFIG_WATCHDOG)
219 204 /* Charge the watchdog timer - prescaler = 64k, count = 64k*/
... ... @@ -222,8 +207,6 @@
222 207  
223 208 reset_5xxx_watchdog();
224 209 #endif /* CONFIG_WATCHDOG */
225   -
226   -#endif /* CONFIG_MPC5200 */
227 210 }
228 211  
229 212 /*
230 213  
... ... @@ -235,11 +218,7 @@
235 218 (struct mpc5xxx_intr *) MPC5XXX_ICTL;
236 219  
237 220 /* mask all interrupts */
238   -#if defined(CONFIG_MGT5100)
239   - out_be32(&intr->per_mask, 0xfffffc00);
240   -#elif defined(CONFIG_MPC5200)
241 221 out_be32(&intr->per_mask, 0xffffff00);
242   -#endif
243 222 setbits_be32(&intr->main_mask, 0x0001ffff);
244 223 clrbits_be32(&intr->ctrl, 0x00000f00);
245 224 /* route critical ints to normal ints */
cpu/mpc5xxx/firmware_sc_task.impl.S
View file @ fd428c0
1   -/*
2   - * Copyright (C) 2001, Software Center, Motorola China.
3   - *
4   - * This file contains microcode for the FEC controller of the MGT5100 CPU.
5   - */
6   -
7   -#include <config.h>
8   -
9   -#if defined(CONFIG_MGT5100)
10   -
11   -/* sas/sccg, gas target */
12   -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */
13   -.section smartdmaTaskTable,"aw",@progbits /* Task tables */
14   -.globl taskTable
15   -taskTable:
16   -.globl scEthernetRecv_Entry
17   -scEthernetRecv_Entry: /* Task 0 */
18   -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */
19   -.long scEthernetRecv_TDT - taskTable + 0x000000a4
20   -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */
21   -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */
22   -.long 0x00000000
23   -.long 0x00000000
24   -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */
25   -.long 0xf0000000
26   -.globl scEthernetXmit_Entry
27   -scEthernetXmit_Entry: /* Task 1 */
28   -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */
29   -.long scEthernetXmit_TDT - taskTable + 0x000000d0
30   -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */
31   -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */
32   -.long 0x00000000
33   -.long 0x00000000
34   -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */
35   -.long 0xf0000000
36   -
37   -
38   -.globl scEthernetRecv_TDT
39   -scEthernetRecv_TDT: /* Task 0 Descriptor Table */
40   -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */
41   -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */
42   -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
43   -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
44   -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */
45   -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
46   -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
47   -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
48   -.long 0x010c504c /* 0020: DRD2B1: var4 = EU1(); EU1(var1,var12) */
49   -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */
50   -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */
51   -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
52   -.long 0x018c504e /* 0030: DRD2B1: var6 = EU1(); EU1(var1,var14) */
53   -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
54   -.long 0x020c504f /* 0038: DRD2B1: var8 = EU1(); EU1(var1,var15) */
55   -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
56   -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */
57   -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */
58   -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */
59   -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
60   -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */
61   -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */
62   -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
63   -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */
64   -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */
65   -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */
66   -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */
67   -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
68   -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */
69   -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */
70   -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */
71   -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
72   -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
73   -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */
74   -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */
75   -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
76   -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */
77   -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
78   -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
79   -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
80   -.long 0x080c504c /* 00A0: DRD2B1: idx0 = EU1(); EU1(var1,var12) */
81   -.long 0x000001f8 /* 00A4(:0): NOP */
82   -
83   -
84   -.globl scEthernetXmit_TDT
85   -scEthernetXmit_TDT: /* Task 1 Descriptor Table */
86   -.long 0x80014800 /* 0000: LCDEXT: idx0 = 0xf0004800; ; */
87   -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */
88   -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
89   -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
90   -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */
91   -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
92   -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
93   -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
94   -.long 0x024c504d /* 0020: DRD2B1: var9 = EU1(); EU1(var1,var13) */
95   -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */
96   -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */
97   -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
98   -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
99   -.long 0x010c504e /* 0034: DRD2B1: var4 = EU1(); EU1(var1,var14) */
100   -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
101   -.long 0x014c504f /* 003C: DRD2B1: var5 = EU1(); EU1(var1,var15) */
102   -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
103   -.long 0x028c5050 /* 0044: DRD2B1: var10 = EU1(); EU1(var1,var16) */
104   -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
105   -.long 0x018c5051 /* 004C: DRD2B1: var6 = EU1(); EU1(var1,var17) */
106   -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
107   -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
108   -.long 0x01cc50a1 /* 0058: DRD2B1: var7 = EU1(); EU1(var2,idx1) */
109   -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */
110   -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */
111   -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */
112   -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */
113   -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */
114   -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */
115   -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */
116   -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */
117   -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */
118   -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */
119   -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
120   -.long 0x60000100 /* 0088: DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
121   -.long 0x0c4c5c4d /* 008C: DRD2B1: *idx1 = EU1(); EU1(*idx1,var13) */
122   -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */
123   -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
124   -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */
125   -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */
126   -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */
127   -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
128   -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
129   -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */
130   -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */
131   -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
132   -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */
133   -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */
134   -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
135   -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
136   -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
137   -.long 0x080c504d /* 00CC: DRD2B1: idx0 = EU1(); EU1(var1,var13) */
138   -.long 0x000001f8 /* 00D0(:0): NOP */
139   -
140   -.align 8
141   -
142   -.globl scEthernetRecv_VarTab
143   -scEthernetRecv_VarTab: /* Task 0 Variable Table */
144   -.long 0x00000000 /* var[0] */
145   -.long 0x00000000 /* var[1] */
146   -.long 0x00000000 /* var[2] */
147   -.long 0x00000000 /* var[3] */
148   -.long 0x00000000 /* var[4] */
149   -.long 0x00000000 /* var[5] */
150   -.long 0x00000000 /* var[6] */
151   -.long 0x00000000 /* var[7] */
152   -.long 0x00000000 /* var[8] */
153   -.long 0xf0004800 /* var[9] */
154   -.long 0x00000008 /* var[10] */
155   -.long 0x0000000c /* var[11] */
156   -.long 0x80000000 /* var[12] */
157   -.long 0x00000000 /* var[13] */
158   -.long 0x10000000 /* var[14] */
159   -.long 0x20000000 /* var[15] */
160   -.long 0x000005e4 /* var[16] */
161   -.long 0x0000000e /* var[17] */
162   -.long 0x000005e0 /* var[18] */
163   -.long 0x00000004 /* var[19] */
164   -.long 0x00000000 /* var[20] */
165   -.long 0x00000000 /* var[21] */
166   -.long 0x00000000 /* var[22] */
167   -.long 0x00000000 /* var[23] */
168   -.long 0x00000000 /* inc[0] */
169   -.long 0x60000000 /* inc[1] */
170   -.long 0x20000001 /* inc[2] */
171   -.long 0x80000000 /* inc[3] */
172   -.long 0x40000000 /* inc[4] */
173   -.long 0x00000000 /* inc[5] */
174   -.long 0x00000000 /* inc[6] */
175   -.long 0x00000000 /* inc[7] */
176   -
177   -.align 8
178   -
179   -.globl scEthernetXmit_VarTab
180   -scEthernetXmit_VarTab: /* Task 1 Variable Table */
181   -.long 0x00000000 /* var[0] */
182   -.long 0x00000000 /* var[1] */
183   -.long 0x00000000 /* var[2] */
184   -.long 0x00000000 /* var[3] */
185   -.long 0x00000000 /* var[4] */
186   -.long 0x00000000 /* var[5] */
187   -.long 0x00000000 /* var[6] */
188   -.long 0x00000000 /* var[7] */
189   -.long 0x00000000 /* var[8] */
190   -.long 0x00000000 /* var[9] */
191   -.long 0x00000000 /* var[10] */
192   -.long 0xf0004800 /* var[11] */
193   -.long 0x00000000 /* var[12] */
194   -.long 0x80000000 /* var[13] */
195   -.long 0x10000000 /* var[14] */
196   -.long 0x08000000 /* var[15] */
197   -.long 0x20000000 /* var[16] */
198   -.long 0x0000ffff /* var[17] */
199   -.long 0xffffffff /* var[18] */
200   -.long 0x00000008 /* var[19] */
201   -.long 0x00000000 /* var[20] */
202   -.long 0x00000000 /* var[21] */
203   -.long 0x00000000 /* var[22] */
204   -.long 0x00000000 /* var[23] */
205   -.long 0x00000000 /* inc[0] */
206   -.long 0x60000000 /* inc[1] */
207   -.long 0x40000000 /* inc[2] */
208   -.long 0x4000ffff /* inc[3] */
209   -.long 0xe0000001 /* inc[4] */
210   -.long 0x80000000 /* inc[5] */
211   -.long 0x00000000 /* inc[6] */
212   -.long 0x00000000 /* inc[7] */
213   -
214   -.align 8
215   -
216   -.globl scEthernetRecv_FDT
217   -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */
218   -.long 0x00000000
219   -.long 0x00000000
220   -.long 0x00000000
221   -.long 0x00000000
222   -.long 0x00000000
223   -.long 0x00000000
224   -.long 0x00000000
225   -.long 0x00000000
226   -.long 0x00000000
227   -.long 0x00000000
228   -.long 0x00000000
229   -.long 0x00000000
230   -.long 0x00000000
231   -.long 0x00000000
232   -.long 0x00000000
233   -.long 0x00000000
234   -.long 0x05800000 /* and(), EU# 1 */
235   -.long 0x05400000 /* andn(), EU# 1 */
236   -.long 0x00000000
237   -.long 0x00000000
238   -.long 0x00000000
239   -.long 0x00000000
240   -.long 0x00000000
241   -.long 0x00000000
242   -.long 0x00000000
243   -.long 0x00000000
244   -.long 0x00000000
245   -.long 0x00000000
246   -.long 0x00000000
247   -.long 0x00000000
248   -.long 0x00000000
249   -.long 0x00000000
250   -.long 0x00000000
251   -.long 0x00000000
252   -.long 0x00000000
253   -.long 0x00000000
254   -.long 0x00000000
255   -.long 0x00000000
256   -.long 0x00000000
257   -.long 0x00000000
258   -.long 0x00000000
259   -.long 0x00000000
260   -.long 0x00000000
261   -.long 0x00000000
262   -.long 0x00000000
263   -.long 0x00000000
264   -.long 0x00000000
265   -.long 0x00000000
266   -.long 0x00000000
267   -.long 0x00000000
268   -.long 0x00000000
269   -.long 0x00000000
270   -.long 0x00000000
271   -.long 0x00000000
272   -.long 0x00000000
273   -.long 0x00000000
274   -.long 0x00000000
275   -.long 0x00000000
276   -.long 0x00000000
277   -.long 0x00000000
278   -.long 0x00000000
279   -.long 0x00000000
280   -.long 0x00000000
281   -.long 0x00000000
282   -
283   -.align 8
284   -
285   -.globl scEthernetXmit_FDT
286   -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */
287   -.long 0x00000000
288   -.long 0x00000000
289   -.long 0x00000000
290   -.long 0x00000000
291   -.long 0x00000000
292   -.long 0x00000000
293   -.long 0x00000000
294   -.long 0x00000000
295   -.long 0x00000000
296   -.long 0x00000000
297   -.long 0x00000000
298   -.long 0x00000000
299   -.long 0x00000000
300   -.long 0x00000000
301   -.long 0x00000000
302   -.long 0x00000000
303   -.long 0x05800000 /* and(), EU# 1 */
304   -.long 0x05400000 /* andn(), EU# 1 */
305   -.long 0x00000000
306   -.long 0x00000000
307   -.long 0x00000000
308   -.long 0x00000000
309   -.long 0x00000000
310   -.long 0x00000000
311   -.long 0x00000000
312   -.long 0x00000000
313   -.long 0x00000000
314   -.long 0x00000000
315   -.long 0x00000000
316   -.long 0x00000000
317   -.long 0x00000000
318   -.long 0x00000000
319   -.long 0x00000000
320   -.long 0x00000000
321   -.long 0x00000000
322   -.long 0x00000000
323   -.long 0x00000000
324   -.long 0x00000000
325   -.long 0x00000000
326   -.long 0x00000000
327   -.long 0x00000000
328   -.long 0x00000000
329   -.long 0x00000000
330   -.long 0x00000000
331   -.long 0x00000000
332   -.long 0x00000000
333   -.long 0x00000000
334   -.long 0x00000000
335   -.long 0x00000000
336   -.long 0x00000000
337   -.long 0x00000000
338   -.long 0x00000000
339   -.long 0x00000000
340   -.long 0x00000000
341   -.long 0x00000000
342   -.long 0x00000000
343   -.long 0x00000000
344   -.long 0x00000000
345   -.long 0x00000000
346   -.long 0x00000000
347   -.long 0x00000000
348   -.long 0x00000000
349   -.long 0x00000000
350   -.long 0x00000000
351   -
352   -
353   -.align 8
354   -.globl scEthernetRecv_CSave
355   -scEthernetRecv_CSave: /* Task 0 context save space */
356   -.space 256, 0x0
357   -
358   -
359   -.align 8
360   -.globl scEthernetXmit_CSave
361   -scEthernetXmit_CSave: /* Task 1 context save space */
362   -.space 256, 0x0
363   -
364   -#endif /* CONFIG_MGT5100 */
cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
Diff comments   View file @ fd428c0
... ... @@ -6,8 +6,6 @@
6 6  
7 7 #include <config.h>
8 8  
9   -#if defined(CONFIG_MPC5200)
10   -
11 9 /* sas/sccg, gas target */
12 10 .section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */
13 11 .section smartdmaTaskTable,"aw",@progbits /* Task tables */
... ... @@ -359,6 +357,4 @@
359 357 .globl scEthernetXmit_CSave
360 358 scEthernetXmit_CSave: /* Task 1 context save space */
361 359 .space 128, 0x0
362   -
363   -#endif /* CONFIG_MPC5200 */
cpu/mpc5xxx/pci_mpc5200.c
Diff comments   View file @ fd428c0
... ... @@ -23,7 +23,7 @@
23 23  
24 24 #include <common.h>
25 25  
26   -#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
  26 +#if defined(CONFIG_PCI)
27 27  
28 28 #include <asm/processor.h>
29 29 #include <asm/io.h>
... ... @@ -184,5 +184,5 @@
184 184  
185 185 hose->last_busno = pci_hose_scan(hose);
186 186 }
187   -#endif /* CONFIG_PCI && CONFIG_MPC5200 */
  187 +#endif /* CONFIG_PCI */
cpu/mpc5xxx/serial.c
Diff comments   View file @ fd428c0
... ... @@ -50,8 +50,6 @@
50 50 #define PSC_BASE MPC5XXX_PSC2
51 51 #elif CONFIG_PSC_CONSOLE == 3
52 52 #define PSC_BASE MPC5XXX_PSC3
53   -#elif defined(CONFIG_MGT5100)
54   -#error CONFIG_PSC_CONSOLE must be in 1, 2 or 3
55 53 #elif CONFIG_PSC_CONSOLE == 4
56 54 #define PSC_BASE MPC5XXX_PSC4
57 55 #elif CONFIG_PSC_CONSOLE == 5
... ... @@ -73,8 +71,6 @@
73 71 #define PSC_BASE2 MPC5XXX_PSC2
74 72 #elif CONFIG_PSC_CONSOLE2 == 3
75 73 #define PSC_BASE2 MPC5XXX_PSC3
76   -#elif defined(CONFIG_MGT5100)
77   -#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3
78 74 #elif CONFIG_PSC_CONSOLE2 == 4
79 75 #define PSC_BASE2 MPC5XXX_PSC4
80 76 #elif CONFIG_PSC_CONSOLE2 == 5
81 77  
82 78  
83 79  
... ... @@ -104,23 +100,14 @@
104 100 psc->command = PSC_SEL_MODE_REG_1;
105 101  
106 102 /* select clock sources */
107   -#if defined(CONFIG_MGT5100)
108   - psc->psc_clock_select = 0xdd00;
109   - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
110   -#elif defined(CONFIG_MPC5200)
111 103 psc->psc_clock_select = 0;
112 104 baseclk = (gd->ipb_clk + 16) / 32;
113   -#endif
114 105  
115 106 /* switch to UART mode */
116 107 psc->sicr = 0;
117 108  
118 109 /* configure parity, bit length and so on */
119   -#if defined(CONFIG_MGT5100)
120   - psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
121   -#elif defined(CONFIG_MPC5200)
122 110 psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
123   -#endif
124 111 psc->mode = PSC_MODE_ONE_STOP;
125 112  
126 113 /* set up UART divisor */
127 114  
... ... @@ -246,11 +233,7 @@
246 233 #endif
247 234 unsigned long baseclk, div;
248 235  
249   -#if defined(CONFIG_MGT5100)
250   - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
251   -#elif defined(CONFIG_MPC5200)
252 236 baseclk = (gd->ipb_clk + 16) / 32;
253   -#endif
254 237  
255 238 /* set up UART divisor */
256 239 div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
... ... @@ -111,9 +111,6 @@
111 111 # if defined(CONFIG_SYS_RAMBOOT)
112 112 # error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
113 113 # endif /* CONFIG_SYS_RAMBOOT */
114   -# if defined(CONFIG_MGT5100)
115   -# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100
116   -# endif /* CONFIG_MGT5100 */
117 114 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
118 115 lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
119 116 ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
120 117  
... ... @@ -145,14 +142,9 @@
145 142 #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
146 143 lis r3, CONFIG_SYS_MBAR@h
147 144 ori r3, r3, CONFIG_SYS_MBAR@l
148   -#if defined(CONFIG_MPC5200)
149 145 /* MBAR is mirrored into the MBAR SPR */
150 146 mtspr MBAR,r3
151 147 rlwinm r3, r3, 16, 16, 31
152   -#endif
153   -#if defined(CONFIG_MGT5100)
154   - rlwinm r3, r3, 17, 15, 31
155   -#endif
156 148 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
157 149 stw r3, 0(r4)
158 150 #endif /* CONFIG_SYS_DEFAULT_MBAR */
cpu/mpc5xxx/usb_ohci.c
Diff comments   View file @ fd428c0
... ... @@ -76,13 +76,8 @@
76 76 #define m16_swap(x) swap_16(x)
77 77 #define m32_swap(x) swap_32(x)
78 78  
79   -#ifdef CONFIG_MPC5200
80 79 #define ohci_cpu_to_le16(x) (x)
81 80 #define ohci_cpu_to_le32(x) (x)
82   -#else
83   -#define ohci_cpu_to_le16(x) swap_16(x)
84   -#define ohci_cpu_to_le32(x) swap_32(x)
85   -#endif
86 81  
87 82 /* global ohci_t */
88 83 static ohci_t gohci;
89 84  
... ... @@ -803,9 +798,7 @@
803 798 } else
804 799 td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
805 800 }
806   -#ifdef CONFIG_MPC5200
807 801 td_list->hwNextTD = 0;
808   -#endif
809 802 }
810 803  
811 804 td_list->next_dl_td = td_rev;
cpu/mpc5xxx/usb_ohci.h
Diff comments   View file @ fd428c0
... ... @@ -127,13 +127,8 @@
127 127 #define NUM_INTS 32 /* part of the OHCI standard */
128 128 struct ohci_hcca {
129 129 __u32 int_table[NUM_INTS]; /* Interrupt ED table */
130   -#if defined(CONFIG_MPC5200)
131 130 __u16 pad1; /* set to 0 on each frame_no change */
132 131 __u16 frame_no; /* current frame number */
133   -#else
134   - __u16 frame_no; /* current frame number */
135   - __u16 pad1; /* set to 0 on each frame_no change */
136   -#endif
137 132 __u32 done_head; /* info returned for an interrupt */
138 133 u8 reserved_for_hc[116];
139 134 } __attribute__((aligned(256)));
drivers/input/ps2ser.c
Diff comments   View file @ fd428c0
... ... @@ -36,8 +36,6 @@
36 36 #define PSC_BASE MPC5XXX_PSC2
37 37 #elif CONFIG_PS2SERIAL == 3
38 38 #define PSC_BASE MPC5XXX_PSC3
39   -#elif defined(CONFIG_MGT5100)
40   -#error CONFIG_PS2SERIAL must be in 1, 2 or 3
41 39 #elif CONFIG_PS2SERIAL == 4
42 40 #define PSC_BASE MPC5XXX_PSC4
43 41 #elif CONFIG_PS2SERIAL == 5
44 42  
45 43  
46 44  
... ... @@ -87,23 +85,14 @@
87 85 psc->command = PSC_SEL_MODE_REG_1;
88 86  
89 87 /* select clock sources */
90   -#if defined(CONFIG_MGT5100)
91   - psc->psc_clock_select = 0xdd00;
92   - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
93   -#elif defined(CONFIG_MPC5200)
94 88 psc->psc_clock_select = 0;
95 89 baseclk = (gd->ipb_clk + 16) / 32;
96   -#endif
97 90  
98 91 /* switch to UART mode */
99 92 psc->sicr = 0;
100 93  
101 94 /* configure parity, bit length and so on */
102   -#if defined(CONFIG_MGT5100)
103   - psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
104   -#elif defined(CONFIG_MPC5200)
105 95 psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
106   -#endif
107 96 psc->mode = PSC_MODE_ONE_STOP;
108 97  
109 98 /* set up UART divisor */
drivers/net/mpc5xxx_fec.c
Diff comments   View file @ fd428c0
... ... @@ -336,13 +336,11 @@
336 336 */
337 337 fec->eth->xmit_fsm = 0x03000000;
338 338  
339   -#if defined(CONFIG_MPC5200)
340 339 /*
341   - * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
  340 + * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
342 341 * work w/ the current receive task.
343 342 */
344 343 sdma->PtdCntrl |= 0x00000001;
345   -#endif
346 344  
347 345 /*
348 346 * Set priority of different initiators
349 347  
... ... @@ -579,9 +577,7 @@
579 577 /********************************************************************/
580 578 static void mpc5xxx_fec_halt(struct eth_device *dev)
581 579 {
582   -#if defined(CONFIG_MPC5200)
583 580 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
584   -#endif
585 581 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
586 582 int counter = 0xffff;
587 583  
588 584  
589 585  
... ... @@ -611,13 +607,11 @@
611 607 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
612 608 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
613 609  
614   -#if defined(CONFIG_MPC5200)
615 610 /*
616   - * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
  611 + * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
617 612 * done. It doesn't work w/ the current receive task.
618 613 */
619 614 sdma->PtdCntrl &= ~0x00000001;
620   -#endif
621 615  
622 616 /*
623 617 * Disable the Ethernet Controller
include/configs/BC3450.h
Diff comments   View file @ fd428c0
... ... @@ -471,13 +471,8 @@
471 471 /*
472 472 * Various low-level settings
473 473 */
474   -#if defined(CONFIG_MPC5200)
475   -# define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
476   -# define CONFIG_SYS_HID0_FINAL HID0_ICE
477   -#else
478   -# define CONFIG_SYS_HID0_INIT 0
479   -# define CONFIG_SYS_HID0_FINAL 0
480   -#endif
  474 +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
  475 +#define CONFIG_SYS_HID0_FINAL HID0_ICE
481 476  
482 477 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
483 478 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/IceCube.h
Diff comments   View file @ fd428c0
... ... @@ -30,6 +30,7 @@
30 30 */
31 31  
32 32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
  33 +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
33 34 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
34 35  
35 36 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
... ... @@ -47,7 +48,6 @@
47 48 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
48 49  
49 50  
50   -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
51 51 /*
52 52 * PCI Mapping:
53 53 * 0x40000000 - 0x4fffffff - PCI Memory
... ... @@ -77,10 +77,6 @@
77 77 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
78 78 #define CONFIG_NS8382X 1
79 79  
80   -#else
81   -#define CONFIG_MII 1
82   -#endif
83   -
84 80 /* Partitions */
85 81 #define CONFIG_MAC_PARTITION
86 82 #define CONFIG_DOS_PARTITION
... ... @@ -169,7 +165,6 @@
169 165  
170 166 #define CONFIG_BOOTCOMMAND "run flash_self"
171 167  
172   -#if defined(CONFIG_MPC5200)
173 168 /*
174 169 * IPB Bus clocking configuration.
175 170 */
... ... @@ -178,7 +173,6 @@
178 173 #else
179 174 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
180 175 #endif
181   -#endif /* CONFIG_MPC5200 */
182 176  
183 177 /* pass open firmware flat tree */
184 178 #define CONFIG_OF_LIBFDT 1
185 179  
... ... @@ -338,13 +332,8 @@
338 332 /*
339 333 * Various low-level settings
340 334 */
341   -#if defined(CONFIG_MPC5200)
342 335 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
343 336 #define CONFIG_SYS_HID0_FINAL HID0_ICE
344   -#else
345   -#define CONFIG_SYS_HID0_INIT 0
346   -#define CONFIG_SYS_HID0_FINAL 0
347   -#endif
348 337  
349 338 #if defined(CONFIG_LITE5200B)
350 339 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
include/configs/PM520.h
Diff comments   View file @ fd428c0
... ... @@ -50,7 +50,6 @@
50 50 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51 51  
52 52  
53   -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
54 53 /*
55 54 * PCI Mapping:
56 55 * 0x40000000 - 0x4fffffff - PCI Memory
... ... @@ -75,7 +74,6 @@
75 74 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
76 75 #undef CONFIG_NS8382X
77 76  
78   -#endif
79 77  
80 78 /* Partitions */
81 79 #define CONFIG_DOS_PARTITION
82 80  
... ... @@ -111,9 +109,7 @@
111 109 #define CONFIG_CMD_SNTP
112 110 #define CONFIG_CMD_USB
113 111  
114   -#if defined(CONFIG_MPC5200)
115 112 #define CONFIG_CMD_PCI
116   -#endif
117 113  
118 114  
119 115 /*
120 116  
... ... @@ -147,12 +143,10 @@
147 143  
148 144 #define CONFIG_BOOTCOMMAND "run flash_self"
149 145  
150   -#if defined(CONFIG_MPC5200)
151 146 /*
152 147 * IPB Bus clocking configuration.
153 148 */
154 149 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
155   -#endif
156 150 /*
157 151 * I2C configuration
158 152 */
159 153  
... ... @@ -301,13 +295,8 @@
301 295 /*
302 296 * Various low-level settings
303 297 */
304   -#if defined(CONFIG_MPC5200)
305 298 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
306 299 #define CONFIG_SYS_HID0_FINAL HID0_ICE
307   -#else
308   -#define CONFIG_SYS_HID0_INIT 0
309   -#define CONFIG_SYS_HID0_FINAL 0
310   -#endif
311 300  
312 301 #if defined(CONFIG_BOOT_ROM)
313 302 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
include/configs/TB5200.h
Diff comments   View file @ fd428c0
... ... @@ -430,13 +430,8 @@
430 430 /*
431 431 * Various low-level settings
432 432 */
433   -#if defined(CONFIG_MPC5200)
434 433 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
435 434 #define CONFIG_SYS_HID0_FINAL HID0_ICE
436   -#else
437   -#define CONFIG_SYS_HID0_INIT 0
438   -#define CONFIG_SYS_HID0_FINAL 0
439   -#endif
440 435  
441 436 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
442 437 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/TQM5200.h
Diff comments   View file @ fd428c0
... ... @@ -633,13 +633,8 @@
633 633 /*
634 634 * Various low-level settings
635 635 */
636   -#if defined(CONFIG_MPC5200)
637 636 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
638 637 #define CONFIG_SYS_HID0_FINAL HID0_ICE
639   -#else
640   -#define CONFIG_SYS_HID0_INIT 0
641   -#define CONFIG_SYS_HID0_FINAL 0
642   -#endif
643 638  
644 639 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
645 640 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/Total5200.h
Diff comments   View file @ fd428c0
... ... @@ -41,6 +41,7 @@
41 41 */
42 42  
43 43 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
  44 +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
44 45 #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
45 46  
46 47 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
... ... @@ -73,7 +74,6 @@
73 74 #define CONFIG_SPLASH_SCREEN
74 75  
75 76  
76   -#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */
77 77 /*
78 78 * PCI Mapping:
79 79 * 0x40000000 - 0x4fffffff - PCI Memory
... ... @@ -98,12 +98,6 @@
98 98 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
99 99 #define CONFIG_NS8382X 1
100 100  
101   -#else /* MGT5100 */
102   -
103   -#define CONFIG_MII 1
104   -
105   -#endif
106   -
107 101 /* Partitions */
108 102 #define CONFIG_MAC_PARTITION
109 103 #define CONFIG_DOS_PARTITION
... ... @@ -127,9 +121,7 @@
127 121 */
128 122 #include <config_cmd_default.h>
129 123  
130   -#if defined(CONFIG_MPC5200)
131   - #define CONFIG_CMD_PCI
132   -#endif
  124 +#define CONFIG_CMD_PCI
133 125  
134 126 #define CONFIG_CMD_BMP
135 127 #define CONFIG_CMD_EEPROM
136 128  
... ... @@ -176,12 +168,10 @@
176 168  
177 169 #define CONFIG_BOOTCOMMAND "run flash_self"
178 170  
179   -#if defined(CONFIG_MPC5200)
180 171 /*
181 172 * IPB Bus clocking configuration.
182 173 */
183 174 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
184   -#endif
185 175  
186 176 /*
187 177 * I2C configuration
188 178  
... ... @@ -326,17 +316,8 @@
326 316 /*
327 317 * Various low-level settings
328 318 */
329   -#if defined(CONFIG_MPC5200)
330 319 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
331 320 #define CONFIG_SYS_HID0_FINAL HID0_ICE
332   -#else
333   -#define CONFIG_SYS_HID0_INIT 0
334   -#define CONFIG_SYS_HID0_FINAL 0
335   -#endif
336   -
337   -#if defined (CONFIG_MGT5100)
338   -# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */
339   -#endif
340 321  
341 322 #if CONFIG_TOTAL5200_REV==1
342 323 # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
include/configs/aev.h
Diff comments   View file @ fd428c0
... ... @@ -362,13 +362,8 @@
362 362 /*
363 363 * Various low-level settings
364 364 */
365   -#if defined(CONFIG_MPC5200)
366 365 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
367 366 #define CONFIG_SYS_HID0_FINAL HID0_ICE
368   -#else
369   -#define CONFIG_SYS_HID0_INIT 0
370   -#define CONFIG_SYS_HID0_FINAL 0
371   -#endif
372 367  
373 368 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
374 369 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/cpci5200.h
Diff comments   View file @ fd428c0
... ... @@ -59,7 +59,6 @@
59 59 #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
60 60 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
61 61  
62   -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
63 62 /*
64 63 * PCI Mapping:
65 64 * 0x40000000 - 0x4fffffff - PCI Memory
... ... @@ -90,8 +89,6 @@
90 89 #define CONFIG_NS8382X 1
91 90 #endif
92 91  
93   -#endif
94   -
95 92 /* Partitions */
96 93 #define CONFIG_MAC_PARTITION
97 94 #define CONFIG_DOS_PARTITION
... ... @@ -169,8 +166,6 @@
169 166  
170 167 #define CONFIG_BOOTCOMMAND "run flash_vxworks0"
171 168  
172   -#if defined(CONFIG_MPC5200)
173   -
174 169 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
175 170 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000
176 171 #define CONFIG_SYS_NVRAM_SIZE 32*1024
... ... @@ -179,7 +174,6 @@
179 174 * IPB Bus clocking configuration.
180 175 */
181 176 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
182   -#endif
183 177 /*
184 178 * I2C configuration
185 179 */
186 180  
... ... @@ -303,13 +297,8 @@
303 297 /*
304 298 * Various low-level settings
305 299 */
306   -#if defined(CONFIG_MPC5200)
307 300 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
308 301 #define CONFIG_SYS_HID0_FINAL HID0_ICE
309   -#else
310   -#define CONFIG_SYS_HID0_INIT 0
311   -#define CONFIG_SYS_HID0_FINAL 0
312   -#endif
313 302  
314 303 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
315 304 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/hmi1001.h
Diff comments   View file @ fd428c0
... ... @@ -261,13 +261,8 @@
261 261 /*
262 262 * Various low-level settings
263 263 */
264   -#if defined(CONFIG_MPC5200)
265 264 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
266 265 #define CONFIG_SYS_HID0_FINAL HID0_ICE
267   -#else
268   -#define CONFIG_SYS_HID0_INIT 0
269   -#define CONFIG_SYS_HID0_FINAL 0
270   -#endif
271 266  
272 267 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
273 268 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/inka4x0.h
Diff comments   View file @ fd428c0
... ... @@ -366,13 +366,8 @@
366 366 /*
367 367 * Various low-level settings
368 368 */
369   -#if defined(CONFIG_MPC5200)
370 369 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
371 370 #define CONFIG_SYS_HID0_FINAL HID0_ICE
372   -#else
373   -#define CONFIG_SYS_HID0_INIT 0
374   -#define CONFIG_SYS_HID0_FINAL 0
375   -#endif
376 371  
377 372 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
378 373 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/ipek01.h
Diff comments   View file @ fd428c0
... ... @@ -324,13 +324,8 @@
324 324 /*
325 325 * Various low-level settings
326 326 */
327   -#if defined(CONFIG_MPC5200)
328 327 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
329 328 #define CONFIG_SYS_HID0_FINAL HID0_ICE
330   -#else
331   -#define CONFIG_SYS_HID0_INIT 0
332   -#define CONFIG_SYS_HID0_FINAL 0
333   -#endif
334 329  
335 330 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
336 331 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/manroland/mpc5200-common.h
Diff comments   View file @ fd428c0
... ... @@ -170,13 +170,8 @@
170 170 /*
171 171 * Various low-level settings
172 172 */
173   -#if defined(CONFIG_MPC5200)
174 173 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
175 174 #define CONFIG_SYS_HID0_FINAL HID0_ICE
176   -#else
177   -#define CONFIG_SYS_HID0_INIT 0
178   -#define CONFIG_SYS_HID0_FINAL 0
179   -#endif
180 175  
181 176 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
182 177 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/mecp5200.h
Diff comments   View file @ fd428c0
... ... @@ -63,9 +63,6 @@
63 63 #endif
64 64 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
65 65  
66   -
67   -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
68   -
69 66 #define CONFIG_MII
70 67 #if 0 /* test-only !!! */
71 68 #define CONFIG_NET_MULTI 1
... ... @@ -74,10 +71,6 @@
74 71 #define CONFIG_NS8382X 1
75 72 #endif
76 73  
77   -#else /* MPC5100 */
78   -
79   -#endif
80   -
81 74 /* Partitions */
82 75 #define CONFIG_MAC_PARTITION
83 76 #define CONFIG_DOS_PARTITION
84 77  
... ... @@ -152,12 +145,10 @@
152 145  
153 146 #define CONFIG_BOOTCOMMAND "run flash_vxworks0"
154 147  
155   -#if defined(CONFIG_MPC5200)
156 148 /*
157 149 * IPB Bus clocking configuration.
158 150 */
159 151 #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
160   -#endif
161 152 /*
162 153 * I2C configuration
163 154 */
164 155  
... ... @@ -288,13 +279,8 @@
288 279 /*
289 280 * Various low-level settings
290 281 */
291   -#if defined(CONFIG_MPC5200)
292 282 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
293 283 #define CONFIG_SYS_HID0_FINAL HID0_ICE
294   -#else
295   -#define CONFIG_SYS_HID0_INIT 0
296   -#define CONFIG_SYS_HID0_FINAL 0
297   -#endif
298 284  
299 285 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
300 286 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/o2dnt.h
Diff comments   View file @ fd428c0
... ... @@ -138,7 +138,6 @@
138 138  
139 139 #define CONFIG_BOOTCOMMAND "run flash_self"
140 140  
141   -#if defined(CONFIG_MPC5200)
142 141 /*
143 142 * IPB Bus clocking configuration.
144 143 */
... ... @@ -154,7 +153,6 @@
154 153 */
155 154 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
156 155 #endif
157   -#endif
158 156  
159 157 /*
160 158 * I2C configuration
161 159  
... ... @@ -276,13 +274,8 @@
276 274 /*
277 275 * Various low-level settings
278 276 */
279   -#if defined(CONFIG_MPC5200)
280 277 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
281 278 #define CONFIG_SYS_HID0_FINAL HID0_ICE
282   -#else
283   -#define CONFIG_SYS_HID0_INIT 0
284   -#define CONFIG_SYS_HID0_FINAL 0
285   -#endif
286 279  
287 280 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
288 281 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/pf5200.h
Diff comments   View file @ fd428c0
... ... @@ -61,7 +61,6 @@
61 61 #endif
62 62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
63 63  
64   -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
65 64 /*
66 65 * PCI Mapping:
67 66 * 0x40000000 - 0x4fffffff - PCI Memory
... ... @@ -87,7 +86,6 @@
87 86 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
88 87 #define CONFIG_NS8382X 1
89 88 #endif
90   -#endif
91 89  
92 90 /* Partitions */
93 91 #define CONFIG_MAC_PARTITION
94 92  
... ... @@ -121,9 +119,7 @@
121 119 #define CONFIG_CMD_I2C
122 120 #define CONFIG_CMD_IDE
123 121  
124   -#ifdef CONFIG_MPC5200
125 122 #define CONFIG_CMD_PCI
126   -#endif
127 123  
128 124  
129 125 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
130 126  
... ... @@ -166,12 +162,10 @@
166 162  
167 163 #define CONFIG_BOOTCOMMAND "run flash_vxworks0"
168 164  
169   -#if defined(CONFIG_MPC5200)
170 165 /*
171 166 * IPB Bus clocking configuration.
172 167 */
173 168 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
174   -#endif
175 169 /*
176 170 * I2C configuration
177 171 */
178 172  
... ... @@ -289,13 +283,8 @@
289 283 /*
290 284 * Various low-level settings
291 285 */
292   -#if defined(CONFIG_MPC5200)
293 286 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
294 287 #define CONFIG_SYS_HID0_FINAL HID0_ICE
295   -#else
296   -#define CONFIG_SYS_HID0_INIT 0
297   -#define CONFIG_SYS_HID0_FINAL 0
298   -#endif
299 288  
300 289 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
301 290 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/smmaco4.h
Diff comments   View file @ fd428c0
... ... @@ -358,13 +358,8 @@
358 358 /*
359 359 * Various low-level settings
360 360 */
361   -#if defined(CONFIG_MPC5200)
362 361 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
363 362 #define CONFIG_SYS_HID0_FINAL HID0_ICE
364   -#else
365   -#define CONFIG_SYS_HID0_INIT 0
366   -#define CONFIG_SYS_HID0_FINAL 0
367   -#endif
368 363  
369 364 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
370 365 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/spieval.h
Diff comments   View file @ fd428c0
... ... @@ -438,13 +438,8 @@
438 438 /*
439 439 * Various low-level settings
440 440 */
441   -#if defined(CONFIG_MPC5200)
442 441 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
443 442 #define CONFIG_SYS_HID0_FINAL HID0_ICE
444   -#else
445   -#define CONFIG_SYS_HID0_INIT 0
446   -#define CONFIG_SYS_HID0_FINAL 0
447   -#endif
448 443  
449 444 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
450 445 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
include/configs/v38b.h
Diff comments   View file @ fd428c0
... ... @@ -170,12 +170,10 @@
170 170  
171 171 #define CONFIG_BOOTCOMMAND "run net_nfs"
172 172  
173   -#if defined(CONFIG_MPC5200)
174 173 /*
175 174 * IPB Bus clocking configuration.
176 175 */
177 176 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
178   -#endif
179 177  
180 178 /*
181 179 * I2C configuration
1 1 /*
2 2 * include/asm-ppc/mpc5xxx.h
3 3 *
4   - * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
  4 + * Prototypes, etc. for the Motorola MPC5xxx
5 5 * embedded cpu chips
6 6 *
7 7 * 2003 (c) MontaVista, Software, Inc.
8 8  
9 9  
10 10  
... ... @@ -33,24 +33,15 @@
33 33 #include <asm/types.h>
34 34  
35 35 /* Processor name */
36   -#if defined(CONFIG_MPC5200)
37 36 #define CPU_ID_STR "MPC5200"
38   -#elif defined(CONFIG_MGT5100)
39   -#define CPU_ID_STR "MGT5100"
40   -#endif
41 37  
42 38 /* Exception offsets (PowerPC standard) */
43 39 #define EXC_OFF_SYS_RESET 0x0100
44 40 #define _START_OFFSET EXC_OFF_SYS_RESET
45 41  
46 42 /* useful macros for manipulating CSx_START/STOP */
47   -#if defined(CONFIG_MGT5100)
48   -#define START_REG(start) ((start) >> 15)
49   -#define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
50   -#elif defined(CONFIG_MPC5200)
51 43 #define START_REG(start) ((start) >> 16)
52 44 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
53   -#endif
54 45  
55 46 /* Internal memory map */
56 47  
57 48  
... ... @@ -70,21 +61,12 @@
70 61 #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050)
71 62 #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054)
72 63  
73   -#if defined(CONFIG_MGT5100)
74   -#define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034)
75   -#define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038)
76   -#define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c)
77   -#define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040)
78   -#define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044)
79   -#define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048)
80   -#elif defined(CONFIG_MPC5200)
81 64 #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058)
82 65 #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c)
83 66 #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060)
84 67 #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064)
85 68 #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034)
86 69 #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038)
87   -#endif
88 70  
89 71 #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100)
90 72 #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200)
91 73  
92 74  
... ... @@ -99,18 +81,12 @@
99 81 #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200)
100 82 #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00)
101 83  
102   -#if defined(CONFIG_MGT5100)
103 84 #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
104   -#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400)
105   -#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800)
106   -#elif defined(CONFIG_MPC5200)
107   -#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
108 85 #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200)
109 86 #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400)
110 87 #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600)
111 88 #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800)
112 89 #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00)
113   -#endif
114 90  
115 91 #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000)
116 92 #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00)
117 93  
118 94  
... ... @@ -118,22 +94,14 @@
118 94 #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00)
119 95 #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40)
120 96  
121   -#if defined(CONFIG_MGT5100)
122   -#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000)
123   -#define MPC5XXX_SRAM_SIZE (8*1024)
124   -#elif defined(CONFIG_MPC5200)
125 97 #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000)
126 98 #define MPC5XXX_SRAM_SIZE (16*1024)
127   -#endif
128 99  
129 100 /* SDRAM Controller */
130 101 #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
131 102 #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
132 103 #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
133 104 #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
134   -#if defined(CONFIG_MGT5100)
135   -#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
136   -#endif
137 105 #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
138 106  
139 107 /* Clock Distribution Module */
140 108  
141 109  
142 110  
... ... @@ -155,19 +123,15 @@
155 123 #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
156 124 #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
157 125 #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
158   -#if defined(CONFIG_MPC5200)
159 126 #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
160 127 #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
161 128 #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
162 129 #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
163   -#endif
164 130  
165   -#if defined(CONFIG_MPC5200)
166 131 /* XLB Arbiter registers */
167 132 #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
168 133 #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
169 134 #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
170   -#endif
171 135  
172 136 /* GPIO registers */
173 137 #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
... ... @@ -242,14 +206,6 @@
242 206 #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
243 207 #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
244 208 #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
245   -#if defined(CONFIG_MGT5100)
246   -#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
247   -#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
248   -#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
249   -#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
250   -#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
251   -#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
252   -#elif defined(CONFIG_MPC5200)
253 209 #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
254 210 #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
255 211 #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
... ... @@ -262,7 +218,6 @@
262 218 #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
263 219 #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
264 220 #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
265   -#endif
266 221  
267 222 /* Interrupt Controller registers */
268 223 #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
269 224  
270 225  
271 226  
272 227  
... ... @@ -495,31 +450,16 @@
495 450 volatile u32 cs4_stop;
496 451 volatile u32 cs5_start; /* 0x002c */
497 452 volatile u32 cs5_stop;
498   -#if defined(CONFIG_MGT5100)
499   - volatile u32 sdram_start; /* 0x0034 */
500   - volatile u32 sdram_stop; /* 0x0038 */
501   - volatile u32 pci1_start; /* 0x003c */
502   - volatile u32 pci1_stop; /* 0x0040 */
503   - volatile u32 pci2_start; /* 0x0044 */
504   - volatile u32 pci2_stop; /* 0x0048 */
505   -#elif defined(CONFIG_MPC5200)
506 453 volatile u32 sdram0; /* 0x0034 */
507 454 volatile u32 sdram1; /* 0x0038 */
508 455 volatile u32 dummy1[4]; /* 0x003c */
509   -#endif
510 456 volatile u32 boot_start; /* 0x004c */
511 457 volatile u32 boot_stop;
512   -#if defined(CONFIG_MGT5100)
513   - volatile u32 addecr; /* 0x0054 */
514   -#elif defined(CONFIG_MPC5200)
515 458 volatile u32 ipbi_ws_ctrl; /* 0x0054 */
516   -#endif
517   -#if defined(CONFIG_MPC5200)
518 459 volatile u32 cs6_start; /* 0x0058 */
519 460 volatile u32 cs6_stop;
520 461 volatile u32 cs7_start; /* 0x0060 */
521 462 volatile u32 cs7_stop;
522   -#endif
523 463 };
524 464  
525 465 /* Clock distribution module */
526 466  
... ... @@ -546,12 +486,7 @@
546 486 volatile u32 ctrl;
547 487 volatile u32 config1;
548 488 volatile u32 config2;
549   -#if defined(CONFIG_MGT5100)
550   - volatile u32 xlbsel;
551   - volatile u32 dummy[31];
552   -#else
553 489 volatile u32 dummy[32];
554   -#endif
555 490 volatile u32 sdelay;
556 491 };
557 492  
558 493  
... ... @@ -564,12 +499,10 @@
564 499 volatile u32 cs5_cfg;
565 500 volatile u32 cs_ctrl;
566 501 volatile u32 cs_status;
567   -#if defined(CONFIG_MPC5200)
568 502 volatile u32 cs6_cfg;
569 503 volatile u32 cs7_cfg;
570 504 volatile u32 cs_burst;
571 505 volatile u32 cs_deadcycle;
572   -#endif
573 506 };
574 507  
575 508