Eric Lee / smarc-uboot

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Commit fd8fbf7fa0b10199ac89cd13cae851149f51accb

Authored by Ye Li
1 parent 81f74e47fc
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATA 

We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock.  If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.

The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.

This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 2 changed files with 14 additions and 4 deletions Inline Diff

board/freescale/mx6qsabreauto/mx6qsabreauto.c
Diff comments   View file @ fd8fbf7
1 /* 1 /*
2 * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <asm/io.h> 10 #include <asm/io.h>
11 #include <asm/arch/clock.h> 11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h> 13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/mx6-pins.h>
15 #include <asm/errno.h> 15 #include <asm/errno.h>
16 #include <asm/gpio.h> 16 #include <asm/gpio.h>
17 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h> 18 #include <asm/imx-common/mxc_i2c.h>
19 #include <asm/imx-common/boot_mode.h> 19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/spi.h> 20 #include <asm/imx-common/spi.h>
21 #include <mmc.h> 21 #include <mmc.h>
22 #include <fsl_esdhc.h> 22 #include <fsl_esdhc.h>
23 #include <miiphy.h> 23 #include <miiphy.h>
24 #include <netdev.h> 24 #include <netdev.h>
25 #include <asm/arch/sys_proto.h> 25 #include <asm/arch/sys_proto.h>
26 #include <i2c.h> 26 #include <i2c.h>
27 #include <asm/arch/mxc_hdmi.h> 27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/imx-common/video.h> 28 #include <asm/imx-common/video.h>
29 #include <asm/arch/crm_regs.h> 29 #include <asm/arch/crm_regs.h>
30 #include <pca953x.h> 30 #include <pca953x.h>
31 #include <power/pmic.h> 31 #include <power/pmic.h>
32 #include <power/pfuze100_pmic.h> 32 #include <power/pfuze100_pmic.h>
33 #include "../common/pfuze.h" 33 #include "../common/pfuze.h"
34 34
35 #ifdef CONFIG_CMD_SATA 35 #ifdef CONFIG_CMD_SATA
36 #include <asm/imx-common/sata.h> 36 #include <asm/imx-common/sata.h>
37 #endif 37 #endif
38 #ifdef CONFIG_FSL_FASTBOOT 38 #ifdef CONFIG_FSL_FASTBOOT
39 #include <fsl_fastboot.h> 39 #include <fsl_fastboot.h>
40 #ifdef CONFIG_ANDROID_RECOVERY 40 #ifdef CONFIG_ANDROID_RECOVERY
41 #include <recovery.h> 41 #include <recovery.h>
42 #endif 42 #endif
43 #endif /*CONFIG_FSL_FASTBOOT*/ 43 #endif /*CONFIG_FSL_FASTBOOT*/
44 44
45 DECLARE_GLOBAL_DATA_PTR; 45 DECLARE_GLOBAL_DATA_PTR;
46 46
47 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 47 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
49 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 49 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50 50
51 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 51 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
52 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 52 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
53 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 53 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54 54
55 /*Need more drive strength for SD1 slot on base board*/ 55 /*Need more drive strength for SD1 slot on base board*/
56 #define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 56 #define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
57 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 57 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
58 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 58 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
59 59
60 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 60 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
62 62
63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
65 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 65 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
66 66
67 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) 67 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
68 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ 68 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
69 PAD_CTL_SRE_FAST) 69 PAD_CTL_SRE_FAST)
70 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) 70 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
71 71
72 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 72 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
73 73
74 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 74 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
75 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 75 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
76 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 76 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
77 77
78 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 78 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
79 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 79 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
80 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 80 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
81 81
82 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 82 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
83 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 83 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
84 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 84 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
85 85
86 #define I2C_PMIC 1 86 #define I2C_PMIC 1
87 87
88 int dram_init(void) 88 int dram_init(void)
89 { 89 {
90 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 90 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
91 91
92 return 0; 92 return 0;
93 } 93 }
94 94
95 static iomux_v3_cfg_t const uart4_pads[] = { 95 static iomux_v3_cfg_t const uart4_pads[] = {
96 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 96 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
97 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 97 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
98 }; 98 };
99 99
100 static iomux_v3_cfg_t const enet_pads[] = { 100 static iomux_v3_cfg_t const enet_pads[] = {
101 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
103 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 104 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 105 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 107 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 108 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
109 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 109 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
110 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 110 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
111 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 111 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 112 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
113 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 113 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 114 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 115 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 116 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 }; 117 };
118 118
119 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ 119 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
120 static struct i2c_pads_info i2c_pad_info1 = { 120 static struct i2c_pads_info i2c_pad_info1 = {
121 .scl = { 121 .scl = {
122 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 122 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
123 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 123 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
124 .gp = IMX_GPIO_NR(2, 30) 124 .gp = IMX_GPIO_NR(2, 30)
125 }, 125 },
126 .sda = { 126 .sda = {
127 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 127 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
128 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, 128 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
129 .gp = IMX_GPIO_NR(4, 13) 129 .gp = IMX_GPIO_NR(4, 13)
130 } 130 }
131 }; 131 };
132 132
133 #ifndef CONFIG_SYS_FLASH_CFI 133 #ifndef CONFIG_SYS_FLASH_CFI
134 /* 134 /*
135 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, 135 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
136 * Compass Sensor, Accelerometer, Res Touch 136 * Compass Sensor, Accelerometer, Res Touch
137 */ 137 */
138 static struct i2c_pads_info i2c_pad_info2 = { 138 static struct i2c_pads_info i2c_pad_info2 = {
139 .scl = { 139 .scl = {
140 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, 140 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
141 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, 141 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
142 .gp = IMX_GPIO_NR(1, 3) 142 .gp = IMX_GPIO_NR(1, 3)
143 }, 143 },
144 .sda = { 144 .sda = {
145 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 145 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
146 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 146 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
147 .gp = IMX_GPIO_NR(3, 18) 147 .gp = IMX_GPIO_NR(3, 18)
148 } 148 }
149 }; 149 };
150 #endif 150 #endif
151 151
152 static iomux_v3_cfg_t const i2c3_pads[] = { 152 static iomux_v3_cfg_t const i2c3_pads[] = {
153 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 153 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
154 }; 154 };
155 155
156 static iomux_v3_cfg_t const port_exp[] = { 156 static iomux_v3_cfg_t const port_exp[] = {
157 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 157 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
158 }; 158 };
159 159
160 /*Define for building port exp gpio, pin starts from 0*/ 160 /*Define for building port exp gpio, pin starts from 0*/
161 #define PORTEXP_IO_NR(chip, pin) \ 161 #define PORTEXP_IO_NR(chip, pin) \
162 ((chip << 5) + pin) 162 ((chip << 5) + pin)
163 163
164 /*Get the chip addr from a ioexp gpio*/ 164 /*Get the chip addr from a ioexp gpio*/
165 #define PORTEXP_IO_TO_CHIP(gpio_nr) \ 165 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
166 (gpio_nr >> 5) 166 (gpio_nr >> 5)
167 167
168 /*Get the pin number from a ioexp gpio*/ 168 /*Get the pin number from a ioexp gpio*/
169 #define PORTEXP_IO_TO_PIN(gpio_nr) \ 169 #define PORTEXP_IO_TO_PIN(gpio_nr) \
170 (gpio_nr & 0x1f) 170 (gpio_nr & 0x1f)
171 171
172 static int port_exp_direction_output(unsigned gpio, int value) 172 static int port_exp_direction_output(unsigned gpio, int value)
173 { 173 {
174 int ret; 174 int ret;
175 175
176 i2c_set_bus_num(2); 176 i2c_set_bus_num(2);
177 ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio)); 177 ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
178 if (ret) 178 if (ret)
179 return ret; 179 return ret;
180 180
181 ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio), 181 ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
182 (1 << PORTEXP_IO_TO_PIN(gpio)), 182 (1 << PORTEXP_IO_TO_PIN(gpio)),
183 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio))); 183 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
184 184
185 if (ret) 185 if (ret)
186 return ret; 186 return ret;
187 187
188 ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio), 188 ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
189 (1 << PORTEXP_IO_TO_PIN(gpio)), 189 (1 << PORTEXP_IO_TO_PIN(gpio)),
190 (value << PORTEXP_IO_TO_PIN(gpio))); 190 (value << PORTEXP_IO_TO_PIN(gpio)));
191 191
192 if (ret) 192 if (ret)
193 return ret; 193 return ret;
194 194
195 return 0; 195 return 0;
196 } 196 }
197 197
198 #ifdef CONFIG_SYS_USE_EIMNOR 198 #ifdef CONFIG_SYS_USE_EIMNOR
199 static iomux_v3_cfg_t const eimnor_pads[] = { 199 static iomux_v3_cfg_t const eimnor_pads[] = {
200 MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 200 MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
201 MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 201 MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
202 MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 202 MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
203 MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 203 MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
204 MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 204 MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
205 MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 205 MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
206 MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 206 MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
207 MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 207 MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
208 MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 208 MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
209 MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 209 MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
210 MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 210 MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
211 MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 211 MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
212 MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 212 MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
213 MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 213 MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
214 MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 214 MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
215 MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 215 MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
216 MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 216 MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
217 MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 217 MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
218 MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 218 MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
219 MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 219 MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
220 MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 220 MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
221 MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 221 MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
222 MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 222 MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
223 MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 223 MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
224 MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 224 MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
225 MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 225 MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
226 MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 226 MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
227 MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , 227 MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
228 MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 228 MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
229 MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 229 MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
230 MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 230 MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
231 MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 231 MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
232 MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 232 MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
233 MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 233 MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
234 MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 234 MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
235 MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 235 MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
236 MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 236 MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
237 MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 237 MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
238 MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 238 MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
239 MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), 239 MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
240 MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 240 MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
241 MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL), 241 MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
242 MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL), 242 MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
243 }; 243 };
244 244
245 static void eimnor_cs_setup(void) 245 static void eimnor_cs_setup(void)
246 { 246 {
247 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; 247 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
248 248
249 writel(0x00020181, &weim_regs->cs0gcr1); 249 writel(0x00020181, &weim_regs->cs0gcr1);
250 writel(0x00000001, &weim_regs->cs0gcr2); 250 writel(0x00000001, &weim_regs->cs0gcr2);
251 writel(0x0a020000, &weim_regs->cs0rcr1); 251 writel(0x0a020000, &weim_regs->cs0rcr1);
252 writel(0x0000c000, &weim_regs->cs0rcr2); 252 writel(0x0000c000, &weim_regs->cs0rcr2);
253 writel(0x0804a240, &weim_regs->cs0wcr1); 253 writel(0x0804a240, &weim_regs->cs0wcr1);
254 writel(0x00000120, &weim_regs->wcr); 254 writel(0x00000120, &weim_regs->wcr);
255 255
256 set_chipselect_size(CS0_128); 256 set_chipselect_size(CS0_128);
257 } 257 }
258 258
259 static void setup_iomux_eimnor(void) 259 static void setup_iomux_eimnor(void)
260 { 260 {
261 imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads)); 261 imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
262 262
263 gpio_direction_output(IMX_GPIO_NR(5, 4), 0); 263 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
264 264
265 eimnor_cs_setup(); 265 eimnor_cs_setup();
266 } 266 }
267 #endif 267 #endif
268 268
269 static void setup_iomux_enet(void) 269 static void setup_iomux_enet(void)
270 { 270 {
271 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 271 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
272 } 272 }
273 273
274 static iomux_v3_cfg_t const usdhc1_pads[] = { 274 static iomux_v3_cfg_t const usdhc1_pads[] = {
275 /*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/ 275 /*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/
276 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC1_PAD_CTRL), 276 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
277 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC1_PAD_CTRL), 277 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
278 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC1_PAD_CTRL), 278 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
279 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC1_PAD_CTRL), 279 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
280 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC1_PAD_CTRL), 280 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
281 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC1_PAD_CTRL), 281 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC1_PAD_CTRL),
282 282
283 /*CD pin*/ 283 /*CD pin*/
284 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), 284 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
285 }; 285 };
286 286
287 static iomux_v3_cfg_t const usdhc3_pads[] = { 287 static iomux_v3_cfg_t const usdhc3_pads[] = {
288 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 288 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
289 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 289 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
290 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 290 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
291 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 291 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
292 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 292 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
293 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 293 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
294 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 294 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
295 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 295 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
296 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 296 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
297 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 297 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
298 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 298 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
299 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 299 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
300 }; 300 };
301 301
302 static void setup_iomux_uart(void) 302 static void setup_iomux_uart(void)
303 { 303 {
304 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 304 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
305 } 305 }
306 306
307 #ifdef CONFIG_FSL_ESDHC 307 #ifdef CONFIG_FSL_ESDHC
308 308
309 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) 309 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
310 #define USDHC3_CD_GPIO IMX_GPIO_NR(6, 15) 310 #define USDHC3_CD_GPIO IMX_GPIO_NR(6, 15)
311 311
312 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 312 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
313 {USDHC1_BASE_ADDR, 0, 4}, 313 {USDHC1_BASE_ADDR, 0, 4},
314 {USDHC3_BASE_ADDR}, 314 {USDHC3_BASE_ADDR},
315 }; 315 };
316 316
317 int board_mmc_get_env_dev(int devno) 317 int board_mmc_get_env_dev(int devno)
318 { 318 {
319 /* 319 /*
320 * need ubstract 1 to map to the mmc3 device id 320 * need ubstract 1 to map to the mmc3 device id
321 * see the comments in board_mmc_init function 321 * see the comments in board_mmc_init function
322 */ 322 */
323 if (devno == 2) 323 if (devno == 2)
324 devno--; 324 devno--;
325 325
326 return devno; 326 return devno;
327 } 327 }
328 328
329 int mmc_map_to_kernel_blk(int devno) 329 int mmc_map_to_kernel_blk(int devno)
330 { 330 {
331 if (devno == 1) 331 if (devno == 1)
332 devno = 2; 332 devno = 2;
333 333
334 return devno; 334 return devno;
335 } 335 }
336 336
337 int board_mmc_getcd(struct mmc *mmc) 337 int board_mmc_getcd(struct mmc *mmc)
338 { 338 {
339 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 339 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
340 int ret = 0; 340 int ret = 0;
341 341
342 switch (cfg->esdhc_base) { 342 switch (cfg->esdhc_base) {
343 case USDHC1_BASE_ADDR: 343 case USDHC1_BASE_ADDR:
344 gpio_direction_input(USDHC1_CD_GPIO); 344 gpio_direction_input(USDHC1_CD_GPIO);
345 ret = !gpio_get_value(USDHC1_CD_GPIO); 345 ret = !gpio_get_value(USDHC1_CD_GPIO);
346 break; 346 break;
347 case USDHC3_BASE_ADDR: 347 case USDHC3_BASE_ADDR:
348 gpio_direction_input(USDHC3_CD_GPIO); 348 gpio_direction_input(USDHC3_CD_GPIO);
349 ret = !gpio_get_value(USDHC3_CD_GPIO); 349 ret = !gpio_get_value(USDHC3_CD_GPIO);
350 break; 350 break;
351 } 351 }
352 352
353 return ret; 353 return ret;
354 } 354 }
355 355
356 int board_mmc_init(bd_t *bis) 356 int board_mmc_init(bd_t *bis)
357 { 357 {
358 int i; 358 int i;
359 359
360 /* 360 /*
361 * According to the board_mmc_init() the following map is done: 361 * According to the board_mmc_init() the following map is done:
362 * (U-boot device node) (Physical Port) 362 * (U-boot device node) (Physical Port)
363 * mmc0 USDHC1 363 * mmc0 USDHC1
364 * mmc1 USDHC3 364 * mmc1 USDHC3
365 */ 365 */
366 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 366 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
367 switch (i) { 367 switch (i) {
368 case 0: 368 case 0:
369 imx_iomux_v3_setup_multiple_pads( 369 imx_iomux_v3_setup_multiple_pads(
370 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 370 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
371 gpio_direction_input(USDHC1_CD_GPIO); 371 gpio_direction_input(USDHC1_CD_GPIO);
372 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 372 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
373 break; 373 break;
374 case 1: 374 case 1:
375 imx_iomux_v3_setup_multiple_pads( 375 imx_iomux_v3_setup_multiple_pads(
376 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 376 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
377 gpio_direction_input(USDHC3_CD_GPIO); 377 gpio_direction_input(USDHC3_CD_GPIO);
378 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 378 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
379 break; 379 break;
380 default: 380 default:
381 printf("Warning: you configured more USDHC controllers" 381 printf("Warning: you configured more USDHC controllers"
382 "(%d) than supported by the board\n", i + 1); 382 "(%d) than supported by the board\n", i + 1);
383 return 0; 383 return 0;
384 } 384 }
385 385
386 if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) 386 if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
387 printf("Warning: failed to initialize mmc dev %d\n", i); 387 printf("Warning: failed to initialize mmc dev %d\n", i);
388 } 388 }
389 389
390 return 0; 390 return 0;
391 } 391 }
392 #endif 392 #endif
393 393
394 #ifdef CONFIG_NAND_MXS 394 #ifdef CONFIG_NAND_MXS
395 static iomux_v3_cfg_t gpmi_pads[] = { 395 static iomux_v3_cfg_t gpmi_pads[] = {
396 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 396 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
397 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 397 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
398 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 398 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
399 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), 399 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
400 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 400 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
401 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 401 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
402 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 402 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
403 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 403 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
404 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 404 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
405 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 405 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
406 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 406 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
407 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 407 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
408 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 408 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
409 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 409 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
410 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 410 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
411 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1), 411 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
412 }; 412 };
413 413
414 static void setup_gpmi_nand(void) 414 static void setup_gpmi_nand(void)
415 { 415 {
416 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 416 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
417 417
418 /* config gpmi nand iomux */ 418 /* config gpmi nand iomux */
419 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 419 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
420 420
421 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 421 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
422 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 422 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
423 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); 423 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
424 424
425 /* enable apbh clock gating */ 425 /* enable apbh clock gating */
426 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 426 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
427 } 427 }
428 #endif 428 #endif
429 429
430 int mx6_rgmii_rework(struct phy_device *phydev) 430 int mx6_rgmii_rework(struct phy_device *phydev)
431 { 431 {
432 unsigned short val; 432 unsigned short val;
433 433
434 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 434 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
435 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 435 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
436 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 436 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
437 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 437 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
438 438
439 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 439 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
440 val &= 0xffe3; 440 val &= 0xffe3;
441 val |= 0x18; 441 val |= 0x18;
442 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 442 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
443 443
444 /* introduce tx clock delay */ 444 /* introduce tx clock delay */
445 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 445 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
446 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 446 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
447 val |= 0x0100; 447 val |= 0x0100;
448 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 448 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
449 449
450 return 0; 450 return 0;
451 } 451 }
452 452
453 int board_phy_config(struct phy_device *phydev) 453 int board_phy_config(struct phy_device *phydev)
454 { 454 {
455 mx6_rgmii_rework(phydev); 455 mx6_rgmii_rework(phydev);
456 456
457 if (phydev->drv->config) 457 if (phydev->drv->config)
458 phydev->drv->config(phydev); 458 phydev->drv->config(phydev);
459 459
460 return 0; 460 return 0;
461 } 461 }
462 462
463 static void setup_fec(void) 463 static void setup_fec(void)
464 { 464 {
465 int ret; 465 int ret;
466 466
467 if (is_mx6dqp()) { 467 if (is_mx6dqp()) {
468 /* 468 /*
469 * select ENET MAC0 TX clock from PLL 469 * select ENET MAC0 TX clock from PLL
470 */ 470 */
471 imx_iomux_set_gpr_register(5, 9, 1, 1); 471 imx_iomux_set_gpr_register(5, 9, 1, 1);
472 } else { 472 } else {
473 imx_iomux_set_gpr_register(1, 21, 1, 1); 473 imx_iomux_set_gpr_register(1, 21, 1, 1);
474 } 474 }
475 475
476 ret = enable_fec_anatop_clock(0, ENET_125MHZ); 476 ret = enable_fec_anatop_clock(0, ENET_125MHZ);
477 if (ret) 477 if (ret)
478 printf("Error fec anatop clock settings!\n"); 478 printf("Error fec anatop clock settings!\n");
479
480 setup_iomux_enet();
481 } 479 }
482 480
483 int board_eth_init(bd_t *bis) 481 int board_eth_init(bd_t *bis)
484 { 482 {
485 setup_fec(); 483 setup_iomux_enet();
486 484
487 return cpu_eth_init(bis); 485 return cpu_eth_init(bis);
488 } 486 }
489 487
490 #define BOARD_REV_B 0x200 488 #define BOARD_REV_B 0x200
491 #define BOARD_REV_A 0x100 489 #define BOARD_REV_A 0x100
492 490
493 static int mx6sabre_rev(void) 491 static int mx6sabre_rev(void)
494 { 492 {
495 /* 493 /*
496 * Get Board ID information from OCOTP_GP1[15:8] 494 * Get Board ID information from OCOTP_GP1[15:8]
497 * i.MX6Q ARD RevA: 0x01 495 * i.MX6Q ARD RevA: 0x01
498 * i.MX6Q ARD RevB: 0x02 496 * i.MX6Q ARD RevB: 0x02
499 */ 497 */
500 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 498 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
501 struct fuse_bank *bank = &ocotp->bank[4]; 499 struct fuse_bank *bank = &ocotp->bank[4];
502 struct fuse_bank4_regs *fuse = 500 struct fuse_bank4_regs *fuse =
503 (struct fuse_bank4_regs *)bank->fuse_regs; 501 (struct fuse_bank4_regs *)bank->fuse_regs;
504 int reg = readl(&fuse->gp1); 502 int reg = readl(&fuse->gp1);
505 int ret; 503 int ret;
506 504
507 switch (reg >> 8 & 0x0F) { 505 switch (reg >> 8 & 0x0F) {
508 case 0x02: 506 case 0x02:
509 ret = BOARD_REV_B; 507 ret = BOARD_REV_B;
510 break; 508 break;
511 case 0x01: 509 case 0x01:
512 default: 510 default:
513 ret = BOARD_REV_A; 511 ret = BOARD_REV_A;
514 break; 512 break;
515 } 513 }
516 514
517 return ret; 515 return ret;
518 } 516 }
519 517
520 u32 get_board_rev(void) 518 u32 get_board_rev(void)
521 { 519 {
522 int rev = mx6sabre_rev(); 520 int rev = mx6sabre_rev();
523 521
524 return (get_cpu_rev() & ~(0xF << 8)) | rev; 522 return (get_cpu_rev() & ~(0xF << 8)) | rev;
525 } 523 }
526 524
527 #if defined(CONFIG_VIDEO_IPUV3) 525 #if defined(CONFIG_VIDEO_IPUV3)
528 static void disable_lvds(struct display_info_t const *dev) 526 static void disable_lvds(struct display_info_t const *dev)
529 { 527 {
530 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 528 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
531 529
532 clrbits_le32(&iomux->gpr[2], 530 clrbits_le32(&iomux->gpr[2],
533 IOMUXC_GPR2_LVDS_CH0_MODE_MASK | 531 IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
534 IOMUXC_GPR2_LVDS_CH1_MODE_MASK); 532 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
535 } 533 }
536 534
537 static void do_enable_hdmi(struct display_info_t const *dev) 535 static void do_enable_hdmi(struct display_info_t const *dev)
538 { 536 {
539 disable_lvds(dev); 537 disable_lvds(dev);
540 imx_enable_hdmi_phy(); 538 imx_enable_hdmi_phy();
541 } 539 }
542 540
543 struct display_info_t const displays[] = {{ 541 struct display_info_t const displays[] = {{
544 .bus = -1, 542 .bus = -1,
545 .addr = 0, 543 .addr = 0,
546 .pixfmt = IPU_PIX_FMT_RGB666, 544 .pixfmt = IPU_PIX_FMT_RGB666,
547 .detect = NULL, 545 .detect = NULL,
548 .enable = NULL, 546 .enable = NULL,
549 .mode = { 547 .mode = {
550 .name = "Hannstar-XGA", 548 .name = "Hannstar-XGA",
551 .refresh = 60, 549 .refresh = 60,
552 .xres = 1024, 550 .xres = 1024,
553 .yres = 768, 551 .yres = 768,
554 .pixclock = 15385, 552 .pixclock = 15385,
555 .left_margin = 220, 553 .left_margin = 220,
556 .right_margin = 40, 554 .right_margin = 40,
557 .upper_margin = 21, 555 .upper_margin = 21,
558 .lower_margin = 7, 556 .lower_margin = 7,
559 .hsync_len = 60, 557 .hsync_len = 60,
560 .vsync_len = 10, 558 .vsync_len = 10,
561 .sync = FB_SYNC_EXT, 559 .sync = FB_SYNC_EXT,
562 .vmode = FB_VMODE_NONINTERLACED 560 .vmode = FB_VMODE_NONINTERLACED
563 } }, { 561 } }, {
564 .bus = -1, 562 .bus = -1,
565 .addr = 0, 563 .addr = 0,
566 .pixfmt = IPU_PIX_FMT_RGB24, 564 .pixfmt = IPU_PIX_FMT_RGB24,
567 .detect = NULL, 565 .detect = NULL,
568 .enable = do_enable_hdmi, 566 .enable = do_enable_hdmi,
569 .mode = { 567 .mode = {
570 .name = "HDMI", 568 .name = "HDMI",
571 .refresh = 60, 569 .refresh = 60,
572 .xres = 640, 570 .xres = 640,
573 .yres = 480, 571 .yres = 480,
574 .pixclock = 39721, 572 .pixclock = 39721,
575 .left_margin = 48, 573 .left_margin = 48,
576 .right_margin = 16, 574 .right_margin = 16,
577 .upper_margin = 33, 575 .upper_margin = 33,
578 .lower_margin = 10, 576 .lower_margin = 10,
579 .hsync_len = 96, 577 .hsync_len = 96,
580 .vsync_len = 2, 578 .vsync_len = 2,
581 .sync = 0, 579 .sync = 0,
582 .vmode = FB_VMODE_NONINTERLACED, 580 .vmode = FB_VMODE_NONINTERLACED,
583 } } }; 581 } } };
584 size_t display_count = ARRAY_SIZE(displays); 582 size_t display_count = ARRAY_SIZE(displays);
585 583
586 iomux_v3_cfg_t const backlight_pads[] = { 584 iomux_v3_cfg_t const backlight_pads[] = {
587 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL), 585 MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
588 }; 586 };
589 587
590 static void setup_iomux_backlight(void) 588 static void setup_iomux_backlight(void)
591 { 589 {
592 gpio_direction_output(IMX_GPIO_NR(2, 9), 1); 590 gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
593 imx_iomux_v3_setup_multiple_pads(backlight_pads, 591 imx_iomux_v3_setup_multiple_pads(backlight_pads,
594 ARRAY_SIZE(backlight_pads)); 592 ARRAY_SIZE(backlight_pads));
595 } 593 }
596 594
597 static void setup_display(void) 595 static void setup_display(void)
598 { 596 {
599 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 597 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
600 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 598 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
601 int reg; 599 int reg;
602 600
603 setup_iomux_backlight(); 601 setup_iomux_backlight();
604 enable_ipu_clock(); 602 enable_ipu_clock();
605 imx_setup_hdmi(); 603 imx_setup_hdmi();
606 604
607 /* Turn on LDB_DI0 and LDB_DI1 clocks */ 605 /* Turn on LDB_DI0 and LDB_DI1 clocks */
608 reg = readl(&mxc_ccm->CCGR3); 606 reg = readl(&mxc_ccm->CCGR3);
609 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; 607 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
610 writel(reg, &mxc_ccm->CCGR3); 608 writel(reg, &mxc_ccm->CCGR3);
611 609
612 /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */ 610 /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
613 reg = readl(&mxc_ccm->cs2cdr); 611 reg = readl(&mxc_ccm->cs2cdr);
614 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | 612 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
615 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 613 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
616 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | 614 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
617 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 615 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
618 writel(reg, &mxc_ccm->cs2cdr); 616 writel(reg, &mxc_ccm->cs2cdr);
619 617
620 reg = readl(&mxc_ccm->cscmr2); 618 reg = readl(&mxc_ccm->cscmr2);
621 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; 619 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
622 writel(reg, &mxc_ccm->cscmr2); 620 writel(reg, &mxc_ccm->cscmr2);
623 621
624 reg = readl(&mxc_ccm->chsccdr); 622 reg = readl(&mxc_ccm->chsccdr);
625 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 623 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
626 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 624 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
627 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << 625 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
628 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); 626 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
629 writel(reg, &mxc_ccm->chsccdr); 627 writel(reg, &mxc_ccm->chsccdr);
630 628
631 reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | 629 reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
632 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | 630 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
633 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | 631 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
634 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | 632 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
635 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | 633 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
636 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 634 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
637 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | 635 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
638 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED; 636 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
639 writel(reg, &iomux->gpr[2]); 637 writel(reg, &iomux->gpr[2]);
640 638
641 reg = readl(&iomux->gpr[3]); 639 reg = readl(&iomux->gpr[3]);
642 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | 640 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
643 IOMUXC_GPR3_HDMI_MUX_CTL_MASK); 641 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
644 reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << 642 reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
645 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | 643 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
646 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << 644 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
647 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET); 645 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
648 writel(reg, &iomux->gpr[3]); 646 writel(reg, &iomux->gpr[3]);
649 } 647 }
650 #endif /* CONFIG_VIDEO_IPUV3 */ 648 #endif /* CONFIG_VIDEO_IPUV3 */
651 649
652 /* 650 /*
653 * Do not overwrite the console 651 * Do not overwrite the console
654 * Use always serial for U-Boot console 652 * Use always serial for U-Boot console
655 */ 653 */
656 int overwrite_console(void) 654 int overwrite_console(void)
657 { 655 {
658 return 1; 656 return 1;
659 } 657 }
660 658
661 #ifdef CONFIG_MXC_SPI 659 #ifdef CONFIG_MXC_SPI
662 iomux_v3_cfg_t const ecspi1_pads[] = { 660 iomux_v3_cfg_t const ecspi1_pads[] = {
663 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 661 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
664 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 662 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
665 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 663 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
666 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 664 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
667 /* Steer logic */ 665 /* Steer logic */
668 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 666 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
669 }; 667 };
670 668
671 void setup_spinor(void) 669 void setup_spinor(void)
672 { 670 {
673 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 671 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
674 ARRAY_SIZE(ecspi1_pads)); 672 ARRAY_SIZE(ecspi1_pads));
675 gpio_direction_output(IMX_GPIO_NR(5, 4), 0); 673 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
676 gpio_direction_output(IMX_GPIO_NR(3, 19), 0); 674 gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
677 } 675 }
678 676
679 int board_spi_cs_gpio(unsigned bus, unsigned cs) 677 int board_spi_cs_gpio(unsigned bus, unsigned cs)
680 { 678 {
681 return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(3, 19)) : -1; 679 return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(3, 19)) : -1;
682 } 680 }
683 #endif 681 #endif
684 682
685 int board_early_init_f(void) 683 int board_early_init_f(void)
686 { 684 {
687 setup_iomux_uart(); 685 setup_iomux_uart();
688 686
689 return 0; 687 return 0;
690 } 688 }
691 689
692 int board_init(void) 690 int board_init(void)
693 { 691 {
694 /* address of boot parameters */ 692 /* address of boot parameters */
695 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 693 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
696 694
697 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */ 695 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
698 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 696 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
699 /* I2C 3 Steer */ 697 /* I2C 3 Steer */
700 gpio_direction_output(IMX_GPIO_NR(5, 4), 1); 698 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
701 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); 699 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
702 #ifndef CONFIG_SYS_FLASH_CFI 700 #ifndef CONFIG_SYS_FLASH_CFI
703 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 701 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
704 #endif 702 #endif
705 gpio_direction_output(IMX_GPIO_NR(1, 15), 1); 703 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
706 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp)); 704 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
707 705
708 #ifdef CONFIG_VIDEO_IPUV3 706 #ifdef CONFIG_VIDEO_IPUV3
709 setup_display(); 707 setup_display();
710 #endif 708 #endif
711 709
712 #ifdef CONFIG_MXC_SPI 710 #ifdef CONFIG_MXC_SPI
713 setup_spinor(); 711 setup_spinor();
714 #endif 712 #endif
715 713
716 #ifdef CONFIG_NAND_MXS 714 #ifdef CONFIG_NAND_MXS
717 setup_gpmi_nand(); 715 setup_gpmi_nand();
718 #endif 716 #endif
719 717
720 #ifdef CONFIG_CMD_SATA 718 #ifdef CONFIG_CMD_SATA
721 setup_sata(); 719 setup_sata();
722 #endif 720 #endif
723 721
724 #ifdef CONFIG_SYS_USE_EIMNOR 722 #ifdef CONFIG_SYS_USE_EIMNOR
725 setup_iomux_eimnor(); 723 setup_iomux_eimnor();
726 #endif 724 #endif
725
726 #ifdef CONFIG_FEC_MXC
727 setup_fec();
728 #endif
729
727 return 0; 730 return 0;
728 } 731 }
729 732
730 int power_init_board(void) 733 int power_init_board(void)
731 { 734 {
732 struct pmic *pfuze; 735 struct pmic *pfuze;
733 unsigned int value; 736 unsigned int value;
734 int ret; 737 int ret;
735 738
736 pfuze = pfuze_common_init(I2C_PMIC); 739 pfuze = pfuze_common_init(I2C_PMIC);
737 if (!pfuze) 740 if (!pfuze)
738 return -ENODEV; 741 return -ENODEV;
739 742
740 if (is_mx6dqp()) 743 if (is_mx6dqp())
741 ret = pfuze_mode_init(pfuze, APS_APS); 744 ret = pfuze_mode_init(pfuze, APS_APS);
742 else 745 else
743 ret = pfuze_mode_init(pfuze, APS_PFM); 746 ret = pfuze_mode_init(pfuze, APS_PFM);
744 747
745 if (ret < 0) 748 if (ret < 0)
746 return ret; 749 return ret;
747 750
748 if (is_mx6dqp()) { 751 if (is_mx6dqp()) {
749 /* set SW1C staby volatage 1.075V*/ 752 /* set SW1C staby volatage 1.075V*/
750 pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); 753 pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
751 value &= ~0x3f; 754 value &= ~0x3f;
752 value |= 0x1f; 755 value |= 0x1f;
753 pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); 756 pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
754 757
755 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ 758 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
756 pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); 759 pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
757 value &= ~0xc0; 760 value &= ~0xc0;
758 value |= 0x40; 761 value |= 0x40;
759 pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); 762 pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
760 763
761 /* set SW2 staby volatage 0.975V*/ 764 /* set SW2 staby volatage 0.975V*/
762 pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value); 765 pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value);
763 value &= ~0x3f; 766 value &= ~0x3f;
764 value |= 0x17; 767 value |= 0x17;
765 pmic_reg_write(pfuze, PFUZE100_SW2STBY, value); 768 pmic_reg_write(pfuze, PFUZE100_SW2STBY, value);
766 769
767 /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ 770 /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
768 pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value); 771 pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value);
769 value &= ~0xc0; 772 value &= ~0xc0;
770 value |= 0x40; 773 value |= 0x40;
771 pmic_reg_write(pfuze, PFUZE100_SW2CONF, value); 774 pmic_reg_write(pfuze, PFUZE100_SW2CONF, value);
772 } else { 775 } else {
773 /* set SW1AB staby volatage 0.975V*/ 776 /* set SW1AB staby volatage 0.975V*/
774 pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); 777 pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
775 value &= ~0x3f; 778 value &= ~0x3f;
776 value |= 0x1b; 779 value |= 0x1b;
777 pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); 780 pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
778 781
779 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 782 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
780 pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); 783 pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
781 value &= ~0xc0; 784 value &= ~0xc0;
782 value |= 0x40; 785 value |= 0x40;
783 pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); 786 pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
784 787
785 /* set SW1C staby volatage 0.975V*/ 788 /* set SW1C staby volatage 0.975V*/
786 pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); 789 pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
787 value &= ~0x3f; 790 value &= ~0x3f;
788 value |= 0x1b; 791 value |= 0x1b;
789 pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); 792 pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
790 793
791 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ 794 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
792 pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); 795 pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
793 value &= ~0xc0; 796 value &= ~0xc0;
794 value |= 0x40; 797 value |= 0x40;
795 pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); 798 pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
796 } 799 }
797 800
798 return 0; 801 return 0;
799 } 802 }
800 803
801 #ifdef CONFIG_LDO_BYPASS_CHECK 804 #ifdef CONFIG_LDO_BYPASS_CHECK
802 void ldo_mode_set(int ldo_bypass) 805 void ldo_mode_set(int ldo_bypass)
803 { 806 {
804 unsigned int value; 807 unsigned int value;
805 struct pmic *p = pmic_get("PFUZE100"); 808 struct pmic *p = pmic_get("PFUZE100");
806 809
807 if (!p) { 810 if (!p) {
808 printf("No PMIC found!\n"); 811 printf("No PMIC found!\n");
809 return; 812 return;
810 } 813 }
811 814
812 /* increase VDDARM/VDDSOC to support 1.2G chip */ 815 /* increase VDDARM/VDDSOC to support 1.2G chip */
813 if (check_1_2G()) { 816 if (check_1_2G()) {
814 ldo_bypass = 0; /* ldo_enable on 1.2G chip */ 817 ldo_bypass = 0; /* ldo_enable on 1.2G chip */
815 printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); 818 printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
816 819
817 if (is_mx6dqp()) { 820 if (is_mx6dqp()) {
818 /* increase VDDARM to 1.425V */ 821 /* increase VDDARM to 1.425V */
819 pmic_reg_read(p, PFUZE100_SW2VOL, &value); 822 pmic_reg_read(p, PFUZE100_SW2VOL, &value);
820 value &= ~0x3f; 823 value &= ~0x3f;
821 value |= 0x29; 824 value |= 0x29;
822 pmic_reg_write(p, PFUZE100_SW2VOL, value); 825 pmic_reg_write(p, PFUZE100_SW2VOL, value);
823 } else { 826 } else {
824 /* increase VDDARM to 1.425V */ 827 /* increase VDDARM to 1.425V */
825 pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); 828 pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
826 value &= ~0x3f; 829 value &= ~0x3f;
827 value |= 0x2d; 830 value |= 0x2d;
828 pmic_reg_write(p, PFUZE100_SW1ABVOL, value); 831 pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
829 } 832 }
830 /* increase VDDSOC to 1.425V */ 833 /* increase VDDSOC to 1.425V */
831 pmic_reg_read(p, PFUZE100_SW1CVOL, &value); 834 pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
832 value &= ~0x3f; 835 value &= ~0x3f;
833 value |= 0x2d; 836 value |= 0x2d;
834 pmic_reg_write(p, PFUZE100_SW1CVOL, value); 837 pmic_reg_write(p, PFUZE100_SW1CVOL, value);
835 } 838 }
836 } 839 }
837 #endif 840 #endif
838 841
839 #ifdef CONFIG_CMD_BMODE 842 #ifdef CONFIG_CMD_BMODE
840 static const struct boot_mode board_boot_modes[] = { 843 static const struct boot_mode board_boot_modes[] = {
841 /* 4 bit bus width */ 844 /* 4 bit bus width */
842 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 845 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
843 {NULL, 0}, 846 {NULL, 0},
844 }; 847 };
845 #endif 848 #endif
846 849
847 int board_late_init(void) 850 int board_late_init(void)
848 { 851 {
849 #ifdef CONFIG_CMD_BMODE 852 #ifdef CONFIG_CMD_BMODE
850 add_board_boot_modes(board_boot_modes); 853 add_board_boot_modes(board_boot_modes);
851 #endif 854 #endif
852 855
853 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 856 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
854 setenv("board_name", "SABREAUTO"); 857 setenv("board_name", "SABREAUTO");
855 858
856 if (is_mx6dqp()) 859 if (is_mx6dqp())
857 setenv("board_rev", "MX6QP"); 860 setenv("board_rev", "MX6QP");
858 else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 861 else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
859 setenv("board_rev", "MX6Q"); 862 setenv("board_rev", "MX6Q");
860 else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) 863 else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
861 setenv("board_rev", "MX6DL"); 864 setenv("board_rev", "MX6DL");
862 #endif 865 #endif
863 866
864 #ifdef CONFIG_ENV_IS_IN_MMC 867 #ifdef CONFIG_ENV_IS_IN_MMC
865 board_late_mmc_env_init(); 868 board_late_mmc_env_init();
866 #endif 869 #endif
867 870
868 return 0; 871 return 0;
869 } 872 }
870 873
871 int checkboard(void) 874 int checkboard(void)
872 { 875 {
873 int rev = mx6sabre_rev(); 876 int rev = mx6sabre_rev();
874 char *revname; 877 char *revname;
875 878
876 switch (rev) { 879 switch (rev) {
877 case BOARD_REV_B: 880 case BOARD_REV_B:
878 revname = "B"; 881 revname = "B";
879 break; 882 break;
880 case BOARD_REV_A: 883 case BOARD_REV_A:
881 default: 884 default:
882 revname = "A"; 885 revname = "A";
883 break; 886 break;
884 } 887 }
885 888
886 printf("Board: MX6Q-Sabreauto rev%s\n", revname); 889 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
887 890
888 return 0; 891 return 0;
889 } 892 }
890 893
891 #ifdef CONFIG_USB_EHCI_MX6 894 #ifdef CONFIG_USB_EHCI_MX6
892 #define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7) 895 #define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
893 #define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1) 896 #define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
894 897
895 iomux_v3_cfg_t const usb_otg_pads[] = { 898 iomux_v3_cfg_t const usb_otg_pads[] = {
896 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), 899 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
897 }; 900 };
898 901
899 int board_ehci_hcd_init(int port) 902 int board_ehci_hcd_init(int port)
900 { 903 {
901 switch (port) { 904 switch (port) {
902 case 0: 905 case 0:
903 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 906 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
904 ARRAY_SIZE(usb_otg_pads)); 907 ARRAY_SIZE(usb_otg_pads));
905 908
906 /* 909 /*
907 * Set daisy chain for otg_pin_id on 6q. 910 * Set daisy chain for otg_pin_id on 6q.
908 * For 6dl, this bit is reserved. 911 * For 6dl, this bit is reserved.
909 */ 912 */
910 imx_iomux_set_gpr_register(1, 13, 1, 0); 913 imx_iomux_set_gpr_register(1, 13, 1, 0);
911 break; 914 break;
912 case 1: 915 case 1:
913 break; 916 break;
914 default: 917 default:
915 printf("MXC USB port %d not yet supported\n", port); 918 printf("MXC USB port %d not yet supported\n", port);
916 return -EINVAL; 919 return -EINVAL;
917 } 920 }
918 return 0; 921 return 0;
919 } 922 }
920 923
921 int board_ehci_power(int port, int on) 924 int board_ehci_power(int port, int on)
922 { 925 {
923 switch (port) { 926 switch (port) {
924 case 0: 927 case 0:
925 if (on) 928 if (on)
926 port_exp_direction_output(USB_OTG_PWR, 1); 929 port_exp_direction_output(USB_OTG_PWR, 1);
927 else 930 else
928 port_exp_direction_output(USB_OTG_PWR, 0); 931 port_exp_direction_output(USB_OTG_PWR, 0);
929 break; 932 break;
930 case 1: 933 case 1:
931 if (on) 934 if (on)
932 port_exp_direction_output(USB_HOST1_PWR, 1); 935 port_exp_direction_output(USB_HOST1_PWR, 1);
933 else 936 else
934 port_exp_direction_output(USB_HOST1_PWR, 0); 937 port_exp_direction_output(USB_HOST1_PWR, 0);
935 break; 938 break;
936 default: 939 default:
937 printf("MXC USB port %d not yet supported\n", port); 940 printf("MXC USB port %d not yet supported\n", port);
938 return -EINVAL; 941 return -EINVAL;
939 } 942 }
940 943
941 return 0; 944 return 0;
942 } 945 }
943 #endif 946 #endif
944 947
945 #ifdef CONFIG_FSL_FASTBOOT 948 #ifdef CONFIG_FSL_FASTBOOT
946 void board_fastboot_setup(void) 949 void board_fastboot_setup(void)
947 { 950 {
948 switch (get_boot_device()) { 951 switch (get_boot_device()) {
949 #if defined(CONFIG_FASTBOOT_STORAGE_SATA) 952 #if defined(CONFIG_FASTBOOT_STORAGE_SATA)
950 case SATA_BOOT: 953 case SATA_BOOT:
951 if (!getenv("fastboot_dev")) 954 if (!getenv("fastboot_dev"))
952 setenv("fastboot_dev", "sata"); 955 setenv("fastboot_dev", "sata");
953 if (!getenv("bootcmd")) 956 if (!getenv("bootcmd"))
954 setenv("bootcmd", "boota sata"); 957 setenv("bootcmd", "boota sata");
955 break; 958 break;
956 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ 959 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
957 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 960 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
958 case SD1_BOOT: 961 case SD1_BOOT:
959 case MMC1_BOOT: 962 case MMC1_BOOT:
960 if (!getenv("fastboot_dev")) 963 if (!getenv("fastboot_dev"))
961 setenv("fastboot_dev", "mmc0"); 964 setenv("fastboot_dev", "mmc0");
962 if (!getenv("bootcmd")) 965 if (!getenv("bootcmd"))
963 setenv("bootcmd", "boota mmc0"); 966 setenv("bootcmd", "boota mmc0");
964 break; 967 break;
965 case SD3_BOOT: 968 case SD3_BOOT:
966 case MMC3_BOOT: 969 case MMC3_BOOT:
967 if (!getenv("fastboot_dev")) 970 if (!getenv("fastboot_dev"))
968 setenv("fastboot_dev", "mmc1"); 971 setenv("fastboot_dev", "mmc1");
969 if (!getenv("bootcmd")) 972 if (!getenv("bootcmd"))
970 setenv("bootcmd", "boota mmc1"); 973 setenv("bootcmd", "boota mmc1");
971 break; 974 break;
972 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 975 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
973 #if defined(CONFIG_FASTBOOT_STORAGE_NAND) 976 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
974 case NAND_BOOT: 977 case NAND_BOOT:
975 if (!getenv("fastboot_dev")) 978 if (!getenv("fastboot_dev"))
976 setenv("fastboot_dev", "nand"); 979 setenv("fastboot_dev", "nand");
977 if (!getenv("fbparts")) 980 if (!getenv("fbparts"))
978 setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS); 981 setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS);
979 if (!getenv("bootcmd")) 982 if (!getenv("bootcmd"))
980 setenv("bootcmd", 983 setenv("bootcmd",
981 "nand read ${loadaddr} ${boot_nand_offset} " 984 "nand read ${loadaddr} ${boot_nand_offset} "
982 "${boot_nand_size};boota ${loadaddr}"); 985 "${boot_nand_size};boota ${loadaddr}");
983 break; 986 break;
984 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/ 987 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
985 default: 988 default:
986 printf("unsupported boot devices\n"); 989 printf("unsupported boot devices\n");
987 break; 990 break;
988 } 991 }
989 } 992 }
990 993
991 #ifdef CONFIG_ANDROID_RECOVERY 994 #ifdef CONFIG_ANDROID_RECOVERY
992 995
993 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 14) 996 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 14)
994 iomux_v3_cfg_t const recovery_key_pads[] = { 997 iomux_v3_cfg_t const recovery_key_pads[] = {
995 (MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), 998 (MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
996 }; 999 };
997 1000
998 int check_recovery_cmd_file(void) 1001 int check_recovery_cmd_file(void)
999 { 1002 {
1000 int button_pressed = 0; 1003 int button_pressed = 0;
1001 int recovery_mode = 0; 1004 int recovery_mode = 0;
1002 1005
1003 recovery_mode = recovery_check_and_clean_flag(); 1006 recovery_mode = recovery_check_and_clean_flag();
1004 1007
1005 /* Check Recovery Combo Button press or not. */ 1008 /* Check Recovery Combo Button press or not. */
1006 imx_iomux_v3_setup_multiple_pads(recovery_key_pads, 1009 imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
1007 ARRAY_SIZE(recovery_key_pads)); 1010 ARRAY_SIZE(recovery_key_pads));
1008 1011
1009 gpio_direction_input(GPIO_VOL_DN_KEY); 1012 gpio_direction_input(GPIO_VOL_DN_KEY);
1010 1013
1011 if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ 1014 if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
1012 button_pressed = 1; 1015 button_pressed = 1;
1013 printf("Recovery key pressed\n"); 1016 printf("Recovery key pressed\n");
1014 } 1017 }
1015 1018
1016 return recovery_mode || button_pressed; 1019 return recovery_mode || button_pressed;
1017 } 1020 }
1018 1021
1019 void board_recovery_setup(void) 1022 void board_recovery_setup(void)
1020 { 1023 {
1021 int bootdev = get_boot_device(); 1024 int bootdev = get_boot_device();
1022 1025
1023 switch (bootdev) { 1026 switch (bootdev) {
1024 #if defined(CONFIG_FASTBOOT_STORAGE_SATA) 1027 #if defined(CONFIG_FASTBOOT_STORAGE_SATA)
1025 case SATA_BOOT: 1028 case SATA_BOOT:
1026 if (!getenv("bootcmd_android_recovery")) 1029 if (!getenv("bootcmd_android_recovery"))
1027 setenv("bootcmd_android_recovery", "boota sata recovery"); 1030 setenv("bootcmd_android_recovery", "boota sata recovery");
1028 break; 1031 break;
1029 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ 1032 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
1030 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 1033 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
1031 case SD1_BOOT: 1034 case SD1_BOOT:
1032 case MMC1_BOOT: 1035 case MMC1_BOOT:
1033 if (!getenv("bootcmd_android_recovery")) 1036 if (!getenv("bootcmd_android_recovery"))
1034 setenv("bootcmd_android_recovery", "boota mmc0 recovery"); 1037 setenv("bootcmd_android_recovery", "boota mmc0 recovery");
1035 break; 1038 break;
1036 case SD3_BOOT: 1039 case SD3_BOOT:
1037 case MMC3_BOOT: 1040 case MMC3_BOOT:
1038 if (!getenv("bootcmd_android_recovery")) 1041 if (!getenv("bootcmd_android_recovery"))
1039 setenv("bootcmd_android_recovery", "boota mmc1 recovery"); 1042 setenv("bootcmd_android_recovery", "boota mmc1 recovery");
1040 break; 1043 break;
1041 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1044 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1042 #if defined(CONFIG_FASTBOOT_STORAGE_NAND) 1045 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
1043 case NAND_BOOT: 1046 case NAND_BOOT:
1044 if (!getenv("bootcmd_android_recovery")) 1047 if (!getenv("bootcmd_android_recovery"))
1045 setenv("bootcmd_android_recovery", 1048 setenv("bootcmd_android_recovery",
1046 "nand read ${loadaddr} ${recovery_nand_offset} " 1049 "nand read ${loadaddr} ${recovery_nand_offset} "
1047 "${recovery_nand_size};boota ${loadaddr}"); 1050 "${recovery_nand_size};boota ${loadaddr}");
1048 break; 1051 break;
1049 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/ 1052 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
1050 default: 1053 default:
1051 printf("Unsupported bootup device for recovery: dev: %d\n", 1054 printf("Unsupported bootup device for recovery: dev: %d\n",
1052 bootdev); 1055 bootdev);
1053 return; 1056 return;
1054 } 1057 }
1055 1058
1056 printf("setup env for recovery..\n"); 1059 printf("setup env for recovery..\n");
1057 setenv("bootcmd", "run bootcmd_android_recovery"); 1060 setenv("bootcmd", "run bootcmd_android_recovery");
1058 } 1061 }
1059 #endif /*CONFIG_ANDROID_RECOVERY*/ 1062 #endif /*CONFIG_ANDROID_RECOVERY*/
1060 1063
1061 #endif /*CONFIG_FSL_FASTBOOT*/ 1064 #endif /*CONFIG_FSL_FASTBOOT*/
board/freescale/mx6sabresd/mx6sabresd.c
Diff comments   View file @ fd8fbf7
1 /* 1 /*
2 * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <asm/arch/clock.h> 9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h> 11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h> 12 #include <asm/arch/mx6-pins.h>
13 #include <asm/errno.h> 13 #include <asm/errno.h>
14 #include <asm/gpio.h> 14 #include <asm/gpio.h>
15 #include <asm/imx-common/mxc_i2c.h> 15 #include <asm/imx-common/mxc_i2c.h>
16 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/imx-common/boot_mode.h> 17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/imx-common/video.h> 18 #include <asm/imx-common/video.h>
19 #include <mmc.h> 19 #include <mmc.h>
20 #include <fsl_esdhc.h> 20 #include <fsl_esdhc.h>
21 #include <miiphy.h> 21 #include <miiphy.h>
22 #include <netdev.h> 22 #include <netdev.h>
23 #include <asm/arch/mxc_hdmi.h> 23 #include <asm/arch/mxc_hdmi.h>
24 #include <asm/arch/crm_regs.h> 24 #include <asm/arch/crm_regs.h>
25 #include <asm/io.h> 25 #include <asm/io.h>
26 #include <asm/arch/sys_proto.h> 26 #include <asm/arch/sys_proto.h>
27 #include <i2c.h> 27 #include <i2c.h>
28 #include <power/pmic.h> 28 #include <power/pmic.h>
29 #include <power/pfuze100_pmic.h> 29 #include <power/pfuze100_pmic.h>
30 #include "../common/pfuze.h" 30 #include "../common/pfuze.h"
31 #include <asm/arch/mx6-ddr.h> 31 #include <asm/arch/mx6-ddr.h>
32 #include <usb.h> 32 #include <usb.h>
33 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) 33 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
34 #include <lcd.h> 34 #include <lcd.h>
35 #include <mxc_epdc_fb.h> 35 #include <mxc_epdc_fb.h>
36 #endif 36 #endif
37 #ifdef CONFIG_CMD_SATA 37 #ifdef CONFIG_CMD_SATA
38 #include <asm/imx-common/sata.h> 38 #include <asm/imx-common/sata.h>
39 #endif 39 #endif
40 #ifdef CONFIG_FSL_FASTBOOT 40 #ifdef CONFIG_FSL_FASTBOOT
41 #include <fsl_fastboot.h> 41 #include <fsl_fastboot.h>
42 #ifdef CONFIG_ANDROID_RECOVERY 42 #ifdef CONFIG_ANDROID_RECOVERY
43 #include <recovery.h> 43 #include <recovery.h>
44 #endif 44 #endif
45 #endif /*CONFIG_FSL_FASTBOOT*/ 45 #endif /*CONFIG_FSL_FASTBOOT*/
46 46
47 DECLARE_GLOBAL_DATA_PTR; 47 DECLARE_GLOBAL_DATA_PTR;
48 48
49 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 49 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
51 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 51 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52 52
53 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 53 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
54 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 54 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
55 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 55 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
56 56
57 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 57 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
58 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 58 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
59 59
60 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 60 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62 62
63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
65 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 65 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
66 66
67 #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ 67 #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
68 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 68 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
69 69
70 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 70 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
71 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 71 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
72 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 72 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
73 73
74 74
75 #define I2C_PMIC 1 75 #define I2C_PMIC 1
76 76
77 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) 77 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
78 78
79 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) 79 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
80 80
81 int dram_init(void) 81 int dram_init(void)
82 { 82 {
83 gd->ram_size = imx_ddr_size(); 83 gd->ram_size = imx_ddr_size();
84 return 0; 84 return 0;
85 } 85 }
86 86
87 static iomux_v3_cfg_t const uart1_pads[] = { 87 static iomux_v3_cfg_t const uart1_pads[] = {
88 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 88 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
89 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 89 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
90 }; 90 };
91 91
92 static iomux_v3_cfg_t const enet_pads[] = { 92 static iomux_v3_cfg_t const enet_pads[] = {
93 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 93 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 94 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 95 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 96 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 97 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 98 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 99 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 100 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
102 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
103 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 104 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 105 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 107 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 /* AR8031 PHY Reset */ 108 /* AR8031 PHY Reset */
109 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 109 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
110 }; 110 };
111 111
112 static void setup_iomux_enet(void) 112 static void setup_iomux_enet(void)
113 { 113 {
114 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 114 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
115 115
116 /* Reset AR8031 PHY */ 116 /* Reset AR8031 PHY */
117 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); 117 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
118 mdelay(10); 118 mdelay(10);
119 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 119 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
120 udelay(100); 120 udelay(100);
121 } 121 }
122 122
123 static iomux_v3_cfg_t const usdhc2_pads[] = { 123 static iomux_v3_cfg_t const usdhc2_pads[] = {
124 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 128 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 129 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 134 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
135 }; 135 };
136 136
137 static iomux_v3_cfg_t const usdhc3_pads[] = { 137 static iomux_v3_cfg_t const usdhc3_pads[] = {
138 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 147 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 148 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
149 }; 149 };
150 150
151 static iomux_v3_cfg_t const usdhc4_pads[] = { 151 static iomux_v3_cfg_t const usdhc4_pads[] = {
152 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 153 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 154 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 155 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 156 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 157 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 158 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 159 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 160 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 161 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 }; 162 };
163 163
164 #ifdef CONFIG_MXC_SPI 164 #ifdef CONFIG_MXC_SPI
165 static iomux_v3_cfg_t const ecspi1_pads[] = { 165 static iomux_v3_cfg_t const ecspi1_pads[] = {
166 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 166 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
167 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 167 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
168 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 168 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
169 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 }; 170 };
171 171
172 static void setup_spi(void) 172 static void setup_spi(void)
173 { 173 {
174 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 174 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
175 } 175 }
176 176
177 int board_spi_cs_gpio(unsigned bus, unsigned cs) 177 int board_spi_cs_gpio(unsigned bus, unsigned cs)
178 { 178 {
179 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; 179 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
180 } 180 }
181 #endif 181 #endif
182 182
183 static iomux_v3_cfg_t const rgb_pads[] = { 183 static iomux_v3_cfg_t const rgb_pads[] = {
184 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), 184 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
185 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), 185 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
186 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL), 186 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
187 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL), 187 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
188 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL), 188 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
189 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 189 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
190 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 190 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
191 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 191 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
192 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 192 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
193 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 193 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
194 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 194 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
195 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 195 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
196 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 196 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
197 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL), 197 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
198 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL), 198 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
199 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL), 199 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
200 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL), 200 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
201 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL), 201 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
202 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL), 202 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
203 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL), 203 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
204 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL), 204 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
205 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL), 205 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
206 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL), 206 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
207 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL), 207 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
208 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL), 208 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
209 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL), 209 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
210 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), 210 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
211 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), 211 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
212 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), 212 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
213 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 213 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
214 }; 214 };
215 215
216 static void enable_rgb(struct display_info_t const *dev) 216 static void enable_rgb(struct display_info_t const *dev)
217 { 217 {
218 imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); 218 imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
219 gpio_direction_output(DISP0_PWR_EN, 1); 219 gpio_direction_output(DISP0_PWR_EN, 1);
220 } 220 }
221 221
222 static struct i2c_pads_info i2c_pad_info1 = { 222 static struct i2c_pads_info i2c_pad_info1 = {
223 .scl = { 223 .scl = {
224 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, 224 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
225 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, 225 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
226 .gp = IMX_GPIO_NR(4, 12) 226 .gp = IMX_GPIO_NR(4, 12)
227 }, 227 },
228 .sda = { 228 .sda = {
229 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, 229 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
230 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, 230 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
231 .gp = IMX_GPIO_NR(4, 13) 231 .gp = IMX_GPIO_NR(4, 13)
232 } 232 }
233 }; 233 };
234 234
235 iomux_v3_cfg_t const pcie_pads[] = { 235 iomux_v3_cfg_t const pcie_pads[] = {
236 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ 236 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
237 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ 237 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
238 }; 238 };
239 239
240 static void setup_pcie(void) 240 static void setup_pcie(void)
241 { 241 {
242 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 242 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
243 } 243 }
244 244
245 iomux_v3_cfg_t const di0_pads[] = { 245 iomux_v3_cfg_t const di0_pads[] = {
246 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ 246 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
247 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ 247 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
248 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ 248 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
249 }; 249 };
250 250
251 static void setup_iomux_uart(void) 251 static void setup_iomux_uart(void)
252 { 252 {
253 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 253 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
254 } 254 }
255 255
256 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) 256 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
257 static iomux_v3_cfg_t const epdc_enable_pads[] = { 257 static iomux_v3_cfg_t const epdc_enable_pads[] = {
258 MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 258 MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
259 MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 259 MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
260 MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 260 MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
261 MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 261 MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
262 MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 262 MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
263 MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 263 MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
264 MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 264 MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
265 MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 265 MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
266 MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), 266 MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
267 MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), 267 MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
268 MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 268 MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
269 MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), 269 MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
270 MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), 270 MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL),
271 MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 271 MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
272 MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), 272 MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
273 MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), 273 MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
274 MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 274 MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
275 MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 275 MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
276 MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 276 MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
277 MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), 277 MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
278 }; 278 };
279 279
280 static iomux_v3_cfg_t const epdc_disable_pads[] = { 280 static iomux_v3_cfg_t const epdc_disable_pads[] = {
281 MX6_PAD_EIM_A16__GPIO2_IO22, 281 MX6_PAD_EIM_A16__GPIO2_IO22,
282 MX6_PAD_EIM_DA10__GPIO3_IO10, 282 MX6_PAD_EIM_DA10__GPIO3_IO10,
283 MX6_PAD_EIM_DA12__GPIO3_IO12, 283 MX6_PAD_EIM_DA12__GPIO3_IO12,
284 MX6_PAD_EIM_DA11__GPIO3_IO11, 284 MX6_PAD_EIM_DA11__GPIO3_IO11,
285 MX6_PAD_EIM_LBA__GPIO2_IO27, 285 MX6_PAD_EIM_LBA__GPIO2_IO27,
286 MX6_PAD_EIM_EB2__GPIO2_IO30, 286 MX6_PAD_EIM_EB2__GPIO2_IO30,
287 MX6_PAD_EIM_CS0__GPIO2_IO23, 287 MX6_PAD_EIM_CS0__GPIO2_IO23,
288 MX6_PAD_EIM_RW__GPIO2_IO26, 288 MX6_PAD_EIM_RW__GPIO2_IO26,
289 MX6_PAD_EIM_A21__GPIO2_IO17, 289 MX6_PAD_EIM_A21__GPIO2_IO17,
290 MX6_PAD_EIM_A22__GPIO2_IO16, 290 MX6_PAD_EIM_A22__GPIO2_IO16,
291 MX6_PAD_EIM_A23__GPIO6_IO06, 291 MX6_PAD_EIM_A23__GPIO6_IO06,
292 MX6_PAD_EIM_A24__GPIO5_IO04, 292 MX6_PAD_EIM_A24__GPIO5_IO04,
293 MX6_PAD_EIM_D31__GPIO3_IO31, 293 MX6_PAD_EIM_D31__GPIO3_IO31,
294 MX6_PAD_EIM_D27__GPIO3_IO27, 294 MX6_PAD_EIM_D27__GPIO3_IO27,
295 MX6_PAD_EIM_DA1__GPIO3_IO01, 295 MX6_PAD_EIM_DA1__GPIO3_IO01,
296 MX6_PAD_EIM_EB1__GPIO2_IO29, 296 MX6_PAD_EIM_EB1__GPIO2_IO29,
297 MX6_PAD_EIM_DA2__GPIO3_IO02, 297 MX6_PAD_EIM_DA2__GPIO3_IO02,
298 MX6_PAD_EIM_DA4__GPIO3_IO04, 298 MX6_PAD_EIM_DA4__GPIO3_IO04,
299 MX6_PAD_EIM_DA5__GPIO3_IO05, 299 MX6_PAD_EIM_DA5__GPIO3_IO05,
300 MX6_PAD_EIM_DA6__GPIO3_IO06, 300 MX6_PAD_EIM_DA6__GPIO3_IO06,
301 }; 301 };
302 #endif 302 #endif
303 303
304 #ifdef CONFIG_FSL_ESDHC 304 #ifdef CONFIG_FSL_ESDHC
305 struct fsl_esdhc_cfg usdhc_cfg[3] = { 305 struct fsl_esdhc_cfg usdhc_cfg[3] = {
306 {USDHC2_BASE_ADDR}, 306 {USDHC2_BASE_ADDR},
307 {USDHC3_BASE_ADDR}, 307 {USDHC3_BASE_ADDR},
308 {USDHC4_BASE_ADDR}, 308 {USDHC4_BASE_ADDR},
309 }; 309 };
310 310
311 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) 311 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
312 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) 312 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
313 313
314 int board_mmc_get_env_dev(int devno) 314 int board_mmc_get_env_dev(int devno)
315 { 315 {
316 return devno - 1; 316 return devno - 1;
317 } 317 }
318 318
319 int mmc_map_to_kernel_blk(int devno) 319 int mmc_map_to_kernel_blk(int devno)
320 { 320 {
321 return devno + 1; 321 return devno + 1;
322 } 322 }
323 323
324 int board_mmc_getcd(struct mmc *mmc) 324 int board_mmc_getcd(struct mmc *mmc)
325 { 325 {
326 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 326 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
327 int ret = 0; 327 int ret = 0;
328 328
329 switch (cfg->esdhc_base) { 329 switch (cfg->esdhc_base) {
330 case USDHC2_BASE_ADDR: 330 case USDHC2_BASE_ADDR:
331 ret = !gpio_get_value(USDHC2_CD_GPIO); 331 ret = !gpio_get_value(USDHC2_CD_GPIO);
332 break; 332 break;
333 case USDHC3_BASE_ADDR: 333 case USDHC3_BASE_ADDR:
334 ret = !gpio_get_value(USDHC3_CD_GPIO); 334 ret = !gpio_get_value(USDHC3_CD_GPIO);
335 break; 335 break;
336 case USDHC4_BASE_ADDR: 336 case USDHC4_BASE_ADDR:
337 ret = 1; /* eMMC/uSDHC4 is always present */ 337 ret = 1; /* eMMC/uSDHC4 is always present */
338 break; 338 break;
339 } 339 }
340 340
341 return ret; 341 return ret;
342 } 342 }
343 343
344 int board_mmc_init(bd_t *bis) 344 int board_mmc_init(bd_t *bis)
345 { 345 {
346 #ifndef CONFIG_SPL_BUILD 346 #ifndef CONFIG_SPL_BUILD
347 int ret; 347 int ret;
348 int i; 348 int i;
349 349
350 /* 350 /*
351 * According to the board_mmc_init() the following map is done: 351 * According to the board_mmc_init() the following map is done:
352 * (U-Boot device node) (Physical Port) 352 * (U-Boot device node) (Physical Port)
353 * mmc0 SD2 353 * mmc0 SD2
354 * mmc1 SD3 354 * mmc1 SD3
355 * mmc2 eMMC 355 * mmc2 eMMC
356 */ 356 */
357 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 357 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
358 switch (i) { 358 switch (i) {
359 case 0: 359 case 0:
360 imx_iomux_v3_setup_multiple_pads( 360 imx_iomux_v3_setup_multiple_pads(
361 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 361 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
362 gpio_direction_input(USDHC2_CD_GPIO); 362 gpio_direction_input(USDHC2_CD_GPIO);
363 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 363 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
364 break; 364 break;
365 case 1: 365 case 1:
366 imx_iomux_v3_setup_multiple_pads( 366 imx_iomux_v3_setup_multiple_pads(
367 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 367 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
368 gpio_direction_input(USDHC3_CD_GPIO); 368 gpio_direction_input(USDHC3_CD_GPIO);
369 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 369 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
370 break; 370 break;
371 case 2: 371 case 2:
372 imx_iomux_v3_setup_multiple_pads( 372 imx_iomux_v3_setup_multiple_pads(
373 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 373 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
374 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 374 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
375 break; 375 break;
376 default: 376 default:
377 printf("Warning: you configured more USDHC controllers" 377 printf("Warning: you configured more USDHC controllers"
378 "(%d) then supported by the board (%d)\n", 378 "(%d) then supported by the board (%d)\n",
379 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 379 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
380 return -EINVAL; 380 return -EINVAL;
381 } 381 }
382 382
383 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 383 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
384 if (ret) 384 if (ret)
385 return ret; 385 return ret;
386 } 386 }
387 387
388 return 0; 388 return 0;
389 #else 389 #else
390 struct src *psrc = (struct src *)SRC_BASE_ADDR; 390 struct src *psrc = (struct src *)SRC_BASE_ADDR;
391 unsigned reg = readl(&psrc->sbmr1) >> 11; 391 unsigned reg = readl(&psrc->sbmr1) >> 11;
392 /* 392 /*
393 * Upon reading BOOT_CFG register the following map is done: 393 * Upon reading BOOT_CFG register the following map is done:
394 * Bit 11 and 12 of BOOT_CFG register can determine the current 394 * Bit 11 and 12 of BOOT_CFG register can determine the current
395 * mmc port 395 * mmc port
396 * 0x1 SD1 396 * 0x1 SD1
397 * 0x2 SD2 397 * 0x2 SD2
398 * 0x3 SD4 398 * 0x3 SD4
399 */ 399 */
400 400
401 switch (reg & 0x3) { 401 switch (reg & 0x3) {
402 case 0x1: 402 case 0x1:
403 imx_iomux_v3_setup_multiple_pads( 403 imx_iomux_v3_setup_multiple_pads(
404 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 404 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
405 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 405 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
406 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 406 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
407 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 407 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
408 break; 408 break;
409 case 0x2: 409 case 0x2:
410 imx_iomux_v3_setup_multiple_pads( 410 imx_iomux_v3_setup_multiple_pads(
411 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 411 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
412 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 412 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
413 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 413 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
414 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 414 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
415 break; 415 break;
416 case 0x3: 416 case 0x3:
417 imx_iomux_v3_setup_multiple_pads( 417 imx_iomux_v3_setup_multiple_pads(
418 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 418 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
419 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 419 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
420 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 420 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
421 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 421 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
422 break; 422 break;
423 } 423 }
424 424
425 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 425 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
426 #endif 426 #endif
427 } 427 }
428 #endif 428 #endif
429 429
430 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) 430 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
431 vidinfo_t panel_info = { 431 vidinfo_t panel_info = {
432 .vl_refresh = 85, 432 .vl_refresh = 85,
433 .vl_col = 800, 433 .vl_col = 800,
434 .vl_row = 600, 434 .vl_row = 600,
435 .vl_pixclock = 26666667, 435 .vl_pixclock = 26666667,
436 .vl_left_margin = 8, 436 .vl_left_margin = 8,
437 .vl_right_margin = 100, 437 .vl_right_margin = 100,
438 .vl_upper_margin = 4, 438 .vl_upper_margin = 4,
439 .vl_lower_margin = 8, 439 .vl_lower_margin = 8,
440 .vl_hsync = 4, 440 .vl_hsync = 4,
441 .vl_vsync = 1, 441 .vl_vsync = 1,
442 .vl_sync = 0, 442 .vl_sync = 0,
443 .vl_mode = 0, 443 .vl_mode = 0,
444 .vl_flag = 0, 444 .vl_flag = 0,
445 .vl_bpix = 3, 445 .vl_bpix = 3,
446 .cmap = 0, 446 .cmap = 0,
447 }; 447 };
448 448
449 struct epdc_timing_params panel_timings = { 449 struct epdc_timing_params panel_timings = {
450 .vscan_holdoff = 4, 450 .vscan_holdoff = 4,
451 .sdoed_width = 10, 451 .sdoed_width = 10,
452 .sdoed_delay = 20, 452 .sdoed_delay = 20,
453 .sdoez_width = 10, 453 .sdoez_width = 10,
454 .sdoez_delay = 20, 454 .sdoez_delay = 20,
455 .gdclk_hp_offs = 419, 455 .gdclk_hp_offs = 419,
456 .gdsp_offs = 20, 456 .gdsp_offs = 20,
457 .gdoe_offs = 0, 457 .gdoe_offs = 0,
458 .gdclk_offs = 5, 458 .gdclk_offs = 5,
459 .num_ce = 1, 459 .num_ce = 1,
460 }; 460 };
461 461
462 static void setup_epdc_power(void) 462 static void setup_epdc_power(void)
463 { 463 {
464 /* Setup epdc voltage */ 464 /* Setup epdc voltage */
465 465
466 /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ 466 /* EIM_A17 - GPIO2[21] for PWR_GOOD status */
467 imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | 467 imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
468 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 468 MUX_PAD_CTRL(EPDC_PAD_CTRL));
469 /* Set as input */ 469 /* Set as input */
470 gpio_direction_input(IMX_GPIO_NR(2, 21)); 470 gpio_direction_input(IMX_GPIO_NR(2, 21));
471 471
472 /* EIM_D17 - GPIO3[17] for VCOM control */ 472 /* EIM_D17 - GPIO3[17] for VCOM control */
473 imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | 473 imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
474 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 474 MUX_PAD_CTRL(EPDC_PAD_CTRL));
475 475
476 /* Set as output */ 476 /* Set as output */
477 gpio_direction_output(IMX_GPIO_NR(3, 17), 1); 477 gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
478 478
479 /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ 479 /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
480 imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | 480 imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
481 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 481 MUX_PAD_CTRL(EPDC_PAD_CTRL));
482 /* Set as output */ 482 /* Set as output */
483 gpio_direction_output(IMX_GPIO_NR(3, 20), 1); 483 gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
484 484
485 /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ 485 /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
486 imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | 486 imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
487 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 487 MUX_PAD_CTRL(EPDC_PAD_CTRL));
488 /* Set as output */ 488 /* Set as output */
489 gpio_direction_output(IMX_GPIO_NR(2, 20), 1); 489 gpio_direction_output(IMX_GPIO_NR(2, 20), 1);
490 } 490 }
491 491
492 static void epdc_enable_pins(void) 492 static void epdc_enable_pins(void)
493 { 493 {
494 /* epdc iomux settings */ 494 /* epdc iomux settings */
495 imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, 495 imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
496 ARRAY_SIZE(epdc_enable_pads)); 496 ARRAY_SIZE(epdc_enable_pads));
497 } 497 }
498 498
499 static void epdc_disable_pins(void) 499 static void epdc_disable_pins(void)
500 { 500 {
501 /* Configure MUX settings for EPDC pins to GPIO */ 501 /* Configure MUX settings for EPDC pins to GPIO */
502 imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, 502 imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
503 ARRAY_SIZE(epdc_disable_pads)); 503 ARRAY_SIZE(epdc_disable_pads));
504 } 504 }
505 505
506 static void setup_epdc(void) 506 static void setup_epdc(void)
507 { 507 {
508 unsigned int reg; 508 unsigned int reg;
509 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 509 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
510 510
511 /*** epdc Maxim PMIC settings ***/ 511 /*** epdc Maxim PMIC settings ***/
512 512
513 /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ 513 /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */
514 imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | 514 imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
515 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 515 MUX_PAD_CTRL(EPDC_PAD_CTRL));
516 516
517 /* EPDC VCOM0 - GPIO3[17] for VCOM control */ 517 /* EPDC VCOM0 - GPIO3[17] for VCOM control */
518 imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | 518 imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
519 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 519 MUX_PAD_CTRL(EPDC_PAD_CTRL));
520 520
521 /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ 521 /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */
522 imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | 522 imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
523 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 523 MUX_PAD_CTRL(EPDC_PAD_CTRL));
524 524
525 /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ 525 /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
526 imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | 526 imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
527 MUX_PAD_CTRL(EPDC_PAD_CTRL)); 527 MUX_PAD_CTRL(EPDC_PAD_CTRL));
528 528
529 /*** Set pixel clock rates for EPDC ***/ 529 /*** Set pixel clock rates for EPDC ***/
530 530
531 /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ 531 /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */
532 reg = readl(&ccm_regs->cscdr3); 532 reg = readl(&ccm_regs->cscdr3);
533 reg &= ~0x7C000; 533 reg &= ~0x7C000;
534 reg |= (1 << 16) | (1 << 14); 534 reg |= (1 << 16) | (1 << 14);
535 writel(reg, &ccm_regs->cscdr3); 535 writel(reg, &ccm_regs->cscdr3);
536 536
537 /* EPDC AXI clk enable */ 537 /* EPDC AXI clk enable */
538 reg = readl(&ccm_regs->CCGR3); 538 reg = readl(&ccm_regs->CCGR3);
539 reg |= 0x00C0; 539 reg |= 0x00C0;
540 writel(reg, &ccm_regs->CCGR3); 540 writel(reg, &ccm_regs->CCGR3);
541 541
542 /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ 542 /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */
543 reg = readl(&ccm_regs->cscdr2); 543 reg = readl(&ccm_regs->cscdr2);
544 reg &= ~0x3FE00; 544 reg &= ~0x3FE00;
545 reg |= (2 << 15) | (5 << 12); 545 reg |= (2 << 15) | (5 << 12);
546 writel(reg, &ccm_regs->cscdr2); 546 writel(reg, &ccm_regs->cscdr2);
547 547
548 /* PLL5 enable (defaults to 650) */ 548 /* PLL5 enable (defaults to 650) */
549 reg = readl(&ccm_regs->analog_pll_video); 549 reg = readl(&ccm_regs->analog_pll_video);
550 reg &= ~((1 << 16) | (1 << 12)); 550 reg &= ~((1 << 16) | (1 << 12));
551 reg |= (1 << 13); 551 reg |= (1 << 13);
552 writel(reg, &ccm_regs->analog_pll_video); 552 writel(reg, &ccm_regs->analog_pll_video);
553 553
554 /* EPDC PIX clk enable */ 554 /* EPDC PIX clk enable */
555 reg = readl(&ccm_regs->CCGR3); 555 reg = readl(&ccm_regs->CCGR3);
556 reg |= 0x0C00; 556 reg |= 0x0C00;
557 writel(reg, &ccm_regs->CCGR3); 557 writel(reg, &ccm_regs->CCGR3);
558 558
559 panel_info.epdc_data.wv_modes.mode_init = 0; 559 panel_info.epdc_data.wv_modes.mode_init = 0;
560 panel_info.epdc_data.wv_modes.mode_du = 1; 560 panel_info.epdc_data.wv_modes.mode_du = 1;
561 panel_info.epdc_data.wv_modes.mode_gc4 = 3; 561 panel_info.epdc_data.wv_modes.mode_gc4 = 3;
562 panel_info.epdc_data.wv_modes.mode_gc8 = 2; 562 panel_info.epdc_data.wv_modes.mode_gc8 = 2;
563 panel_info.epdc_data.wv_modes.mode_gc16 = 2; 563 panel_info.epdc_data.wv_modes.mode_gc16 = 2;
564 panel_info.epdc_data.wv_modes.mode_gc32 = 2; 564 panel_info.epdc_data.wv_modes.mode_gc32 = 2;
565 565
566 panel_info.epdc_data.epdc_timings = panel_timings; 566 panel_info.epdc_data.epdc_timings = panel_timings;
567 567
568 setup_epdc_power(); 568 setup_epdc_power();
569 } 569 }
570 570
571 void epdc_power_on(void) 571 void epdc_power_on(void)
572 { 572 {
573 unsigned int reg; 573 unsigned int reg;
574 struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; 574 struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
575 575
576 /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ 576 /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
577 gpio_set_value(IMX_GPIO_NR(2, 20), 1); 577 gpio_set_value(IMX_GPIO_NR(2, 20), 1);
578 udelay(1000); 578 udelay(1000);
579 579
580 /* Enable epdc signal pin */ 580 /* Enable epdc signal pin */
581 epdc_enable_pins(); 581 epdc_enable_pins();
582 582
583 /* Set PMIC Wakeup to high - enable Display power */ 583 /* Set PMIC Wakeup to high - enable Display power */
584 gpio_set_value(IMX_GPIO_NR(3, 20), 1); 584 gpio_set_value(IMX_GPIO_NR(3, 20), 1);
585 585
586 /* Wait for PWRGOOD == 1 */ 586 /* Wait for PWRGOOD == 1 */
587 while (1) { 587 while (1) {
588 reg = readl(&gpio_regs->gpio_psr); 588 reg = readl(&gpio_regs->gpio_psr);
589 if (!(reg & (1 << 21))) 589 if (!(reg & (1 << 21)))
590 break; 590 break;
591 591
592 udelay(100); 592 udelay(100);
593 } 593 }
594 594
595 /* Enable VCOM */ 595 /* Enable VCOM */
596 gpio_set_value(IMX_GPIO_NR(3, 17), 1); 596 gpio_set_value(IMX_GPIO_NR(3, 17), 1);
597 597
598 udelay(500); 598 udelay(500);
599 } 599 }
600 600
601 void epdc_power_off(void) 601 void epdc_power_off(void)
602 { 602 {
603 /* Set PMIC Wakeup to low - disable Display power */ 603 /* Set PMIC Wakeup to low - disable Display power */
604 gpio_set_value(IMX_GPIO_NR(3, 20), 0); 604 gpio_set_value(IMX_GPIO_NR(3, 20), 0);
605 605
606 /* Disable VCOM */ 606 /* Disable VCOM */
607 gpio_set_value(IMX_GPIO_NR(3, 17), 0); 607 gpio_set_value(IMX_GPIO_NR(3, 17), 0);
608 608
609 epdc_disable_pins(); 609 epdc_disable_pins();
610 610
611 /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ 611 /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
612 gpio_set_value(IMX_GPIO_NR(2, 20), 0); 612 gpio_set_value(IMX_GPIO_NR(2, 20), 0);
613 } 613 }
614 #endif 614 #endif
615 615
616 int mx6_rgmii_rework(struct phy_device *phydev) 616 int mx6_rgmii_rework(struct phy_device *phydev)
617 { 617 {
618 unsigned short val; 618 unsigned short val;
619 619
620 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 620 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
621 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 621 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
622 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 622 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
623 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 623 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
624 624
625 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 625 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
626 val &= 0xffe3; 626 val &= 0xffe3;
627 val |= 0x18; 627 val |= 0x18;
628 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 628 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
629 629
630 /* introduce tx clock delay */ 630 /* introduce tx clock delay */
631 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 631 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
632 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 632 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
633 val |= 0x0100; 633 val |= 0x0100;
634 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 634 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
635 635
636 return 0; 636 return 0;
637 } 637 }
638 638
639 int board_phy_config(struct phy_device *phydev) 639 int board_phy_config(struct phy_device *phydev)
640 { 640 {
641 mx6_rgmii_rework(phydev); 641 mx6_rgmii_rework(phydev);
642 642
643 if (phydev->drv->config) 643 if (phydev->drv->config)
644 phydev->drv->config(phydev); 644 phydev->drv->config(phydev);
645 645
646 return 0; 646 return 0;
647 } 647 }
648 648
649 #if defined(CONFIG_VIDEO_IPUV3) 649 #if defined(CONFIG_VIDEO_IPUV3)
650 static void disable_lvds(struct display_info_t const *dev) 650 static void disable_lvds(struct display_info_t const *dev)
651 { 651 {
652 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 652 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
653 653
654 int reg = readl(&iomux->gpr[2]); 654 int reg = readl(&iomux->gpr[2]);
655 655
656 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | 656 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
657 IOMUXC_GPR2_LVDS_CH1_MODE_MASK); 657 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
658 658
659 writel(reg, &iomux->gpr[2]); 659 writel(reg, &iomux->gpr[2]);
660 } 660 }
661 661
662 static void do_enable_hdmi(struct display_info_t const *dev) 662 static void do_enable_hdmi(struct display_info_t const *dev)
663 { 663 {
664 disable_lvds(dev); 664 disable_lvds(dev);
665 imx_enable_hdmi_phy(); 665 imx_enable_hdmi_phy();
666 } 666 }
667 667
668 static void enable_lvds(struct display_info_t const *dev) 668 static void enable_lvds(struct display_info_t const *dev)
669 { 669 {
670 struct iomuxc *iomux = (struct iomuxc *) 670 struct iomuxc *iomux = (struct iomuxc *)
671 IOMUXC_BASE_ADDR; 671 IOMUXC_BASE_ADDR;
672 u32 reg = readl(&iomux->gpr[2]); 672 u32 reg = readl(&iomux->gpr[2]);
673 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 673 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
674 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; 674 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
675 writel(reg, &iomux->gpr[2]); 675 writel(reg, &iomux->gpr[2]);
676 } 676 }
677 677
678 struct display_info_t const displays[] = {{ 678 struct display_info_t const displays[] = {{
679 .bus = -1, 679 .bus = -1,
680 .addr = 0, 680 .addr = 0,
681 .pixfmt = IPU_PIX_FMT_RGB666, 681 .pixfmt = IPU_PIX_FMT_RGB666,
682 .detect = NULL, 682 .detect = NULL,
683 .enable = enable_lvds, 683 .enable = enable_lvds,
684 .mode = { 684 .mode = {
685 .name = "Hannstar-XGA", 685 .name = "Hannstar-XGA",
686 .refresh = 60, 686 .refresh = 60,
687 .xres = 1024, 687 .xres = 1024,
688 .yres = 768, 688 .yres = 768,
689 .pixclock = 15385, 689 .pixclock = 15385,
690 .left_margin = 220, 690 .left_margin = 220,
691 .right_margin = 40, 691 .right_margin = 40,
692 .upper_margin = 21, 692 .upper_margin = 21,
693 .lower_margin = 7, 693 .lower_margin = 7,
694 .hsync_len = 60, 694 .hsync_len = 60,
695 .vsync_len = 10, 695 .vsync_len = 10,
696 .sync = FB_SYNC_EXT, 696 .sync = FB_SYNC_EXT,
697 .vmode = FB_VMODE_NONINTERLACED 697 .vmode = FB_VMODE_NONINTERLACED
698 } }, { 698 } }, {
699 .bus = -1, 699 .bus = -1,
700 .addr = 0, 700 .addr = 0,
701 .pixfmt = IPU_PIX_FMT_RGB24, 701 .pixfmt = IPU_PIX_FMT_RGB24,
702 .detect = NULL, 702 .detect = NULL,
703 .enable = do_enable_hdmi, 703 .enable = do_enable_hdmi,
704 .mode = { 704 .mode = {
705 .name = "HDMI", 705 .name = "HDMI",
706 .refresh = 60, 706 .refresh = 60,
707 .xres = 640, 707 .xres = 640,
708 .yres = 480, 708 .yres = 480,
709 .pixclock = 39721, 709 .pixclock = 39721,
710 .left_margin = 48, 710 .left_margin = 48,
711 .right_margin = 16, 711 .right_margin = 16,
712 .upper_margin = 33, 712 .upper_margin = 33,
713 .lower_margin = 10, 713 .lower_margin = 10,
714 .hsync_len = 96, 714 .hsync_len = 96,
715 .vsync_len = 2, 715 .vsync_len = 2,
716 .sync = 0, 716 .sync = 0,
717 .vmode = FB_VMODE_NONINTERLACED 717 .vmode = FB_VMODE_NONINTERLACED
718 } }, { 718 } }, {
719 .bus = 0, 719 .bus = 0,
720 .addr = 0, 720 .addr = 0,
721 .pixfmt = IPU_PIX_FMT_RGB24, 721 .pixfmt = IPU_PIX_FMT_RGB24,
722 .detect = NULL, 722 .detect = NULL,
723 .enable = enable_rgb, 723 .enable = enable_rgb,
724 .mode = { 724 .mode = {
725 .name = "SEIKO-WVGA", 725 .name = "SEIKO-WVGA",
726 .refresh = 60, 726 .refresh = 60,
727 .xres = 800, 727 .xres = 800,
728 .yres = 480, 728 .yres = 480,
729 .pixclock = 29850, 729 .pixclock = 29850,
730 .left_margin = 89, 730 .left_margin = 89,
731 .right_margin = 164, 731 .right_margin = 164,
732 .upper_margin = 23, 732 .upper_margin = 23,
733 .lower_margin = 10, 733 .lower_margin = 10,
734 .hsync_len = 10, 734 .hsync_len = 10,
735 .vsync_len = 10, 735 .vsync_len = 10,
736 .sync = 0, 736 .sync = 0,
737 .vmode = FB_VMODE_NONINTERLACED 737 .vmode = FB_VMODE_NONINTERLACED
738 } } }; 738 } } };
739 size_t display_count = ARRAY_SIZE(displays); 739 size_t display_count = ARRAY_SIZE(displays);
740 740
741 static void setup_display(void) 741 static void setup_display(void)
742 { 742 {
743 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 743 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
744 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 744 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
745 int reg; 745 int reg;
746 746
747 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ 747 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
748 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); 748 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
749 749
750 enable_ipu_clock(); 750 enable_ipu_clock();
751 imx_setup_hdmi(); 751 imx_setup_hdmi();
752 752
753 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ 753 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
754 reg = readl(&mxc_ccm->CCGR3); 754 reg = readl(&mxc_ccm->CCGR3);
755 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; 755 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
756 writel(reg, &mxc_ccm->CCGR3); 756 writel(reg, &mxc_ccm->CCGR3);
757 757
758 /* set LDB0, LDB1 clk select to 011/011 */ 758 /* set LDB0, LDB1 clk select to 011/011 */
759 reg = readl(&mxc_ccm->cs2cdr); 759 reg = readl(&mxc_ccm->cs2cdr);
760 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 760 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
761 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 761 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
762 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 762 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
763 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 763 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
764 writel(reg, &mxc_ccm->cs2cdr); 764 writel(reg, &mxc_ccm->cs2cdr);
765 765
766 reg = readl(&mxc_ccm->cscmr2); 766 reg = readl(&mxc_ccm->cscmr2);
767 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; 767 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
768 writel(reg, &mxc_ccm->cscmr2); 768 writel(reg, &mxc_ccm->cscmr2);
769 769
770 reg = readl(&mxc_ccm->chsccdr); 770 reg = readl(&mxc_ccm->chsccdr);
771 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 771 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
772 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 772 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
773 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 773 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
774 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); 774 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
775 writel(reg, &mxc_ccm->chsccdr); 775 writel(reg, &mxc_ccm->chsccdr);
776 776
777 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 777 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
778 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW 778 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
779 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 779 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
780 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 780 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
781 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 781 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
782 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 782 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
783 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 783 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
784 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED 784 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
785 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; 785 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
786 writel(reg, &iomux->gpr[2]); 786 writel(reg, &iomux->gpr[2]);
787 787
788 reg = readl(&iomux->gpr[3]); 788 reg = readl(&iomux->gpr[3]);
789 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK 789 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
790 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 790 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
791 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 791 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
792 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); 792 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
793 writel(reg, &iomux->gpr[3]); 793 writel(reg, &iomux->gpr[3]);
794 } 794 }
795 #endif /* CONFIG_VIDEO_IPUV3 */ 795 #endif /* CONFIG_VIDEO_IPUV3 */
796 796
797 /* 797 /*
798 * Do not overwrite the console 798 * Do not overwrite the console
799 * Use always serial for U-Boot console 799 * Use always serial for U-Boot console
800 */ 800 */
801 int overwrite_console(void) 801 int overwrite_console(void)
802 { 802 {
803 return 1; 803 return 1;
804 } 804 }
805 805
806 int board_eth_init(bd_t *bis) 806 static void setup_fec(void)
807 { 807 {
808 if (is_mx6dqp()) { 808 if (is_mx6dqp()) {
809 int ret; 809 int ret;
810 810
811 /* select ENET MAC0 TX clock from PLL */ 811 /* select ENET MAC0 TX clock from PLL */
812 imx_iomux_set_gpr_register(5, 9, 1, 1); 812 imx_iomux_set_gpr_register(5, 9, 1, 1);
813 ret = enable_fec_anatop_clock(0, ENET_125MHZ); 813 ret = enable_fec_anatop_clock(0, ENET_125MHZ);
814 if (ret) 814 if (ret)
815 printf("Error fec anatop clock settings!\n"); 815 printf("Error fec anatop clock settings!\n");
816 } 816 }
817 }
817 818
819 int board_eth_init(bd_t *bis)
820 {
818 setup_iomux_enet(); 821 setup_iomux_enet();
819 setup_pcie(); 822 setup_pcie();
820 823
821 return cpu_eth_init(bis); 824 return cpu_eth_init(bis);
822 } 825 }
823 826
824 #ifdef CONFIG_USB_EHCI_MX6 827 #ifdef CONFIG_USB_EHCI_MX6
825 #define USB_OTHERREGS_OFFSET 0x800 828 #define USB_OTHERREGS_OFFSET 0x800
826 #define UCTRL_PWR_POL (1 << 9) 829 #define UCTRL_PWR_POL (1 << 9)
827 830
828 static iomux_v3_cfg_t const usb_otg_pads[] = { 831 static iomux_v3_cfg_t const usb_otg_pads[] = {
829 MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 832 MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
830 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), 833 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
831 }; 834 };
832 835
833 static iomux_v3_cfg_t const usb_hc1_pads[] = { 836 static iomux_v3_cfg_t const usb_hc1_pads[] = {
834 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 837 MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
835 }; 838 };
836 839
837 static void setup_usb(void) 840 static void setup_usb(void)
838 { 841 {
839 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 842 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
840 ARRAY_SIZE(usb_otg_pads)); 843 ARRAY_SIZE(usb_otg_pads));
841 844
842 /* 845 /*
843 * set daisy chain for otg_pin_id on 6q. 846 * set daisy chain for otg_pin_id on 6q.
844 * for 6dl, this bit is reserved 847 * for 6dl, this bit is reserved
845 */ 848 */
846 imx_iomux_set_gpr_register(1, 13, 1, 0); 849 imx_iomux_set_gpr_register(1, 13, 1, 0);
847 850
848 imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, 851 imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
849 ARRAY_SIZE(usb_hc1_pads)); 852 ARRAY_SIZE(usb_hc1_pads));
850 } 853 }
851 854
852 int board_ehci_hcd_init(int port) 855 int board_ehci_hcd_init(int port)
853 { 856 {
854 u32 *usbnc_usb_ctrl; 857 u32 *usbnc_usb_ctrl;
855 858
856 if (port > 1) 859 if (port > 1)
857 return -EINVAL; 860 return -EINVAL;
858 861
859 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 862 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
860 port * 4); 863 port * 4);
861 864
862 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 865 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
863 866
864 return 0; 867 return 0;
865 } 868 }
866 869
867 int board_ehci_power(int port, int on) 870 int board_ehci_power(int port, int on)
868 { 871 {
869 switch (port) { 872 switch (port) {
870 case 0: 873 case 0:
871 break; 874 break;
872 case 1: 875 case 1:
873 if (on) 876 if (on)
874 gpio_direction_output(IMX_GPIO_NR(1, 29), 1); 877 gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
875 else 878 else
876 gpio_direction_output(IMX_GPIO_NR(1, 29), 0); 879 gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
877 break; 880 break;
878 default: 881 default:
879 printf("MXC USB port %d not yet supported\n", port); 882 printf("MXC USB port %d not yet supported\n", port);
880 return -EINVAL; 883 return -EINVAL;
881 } 884 }
882 885
883 return 0; 886 return 0;
884 } 887 }
885 #endif 888 #endif
886 889
887 int board_early_init_f(void) 890 int board_early_init_f(void)
888 { 891 {
889 setup_iomux_uart(); 892 setup_iomux_uart();
890 #if defined(CONFIG_VIDEO_IPUV3) 893 #if defined(CONFIG_VIDEO_IPUV3)
891 setup_display(); 894 setup_display();
892 #endif 895 #endif
893 896
894 return 0; 897 return 0;
895 } 898 }
896 899
897 int board_init(void) 900 int board_init(void)
898 { 901 {
899 /* address of boot parameters */ 902 /* address of boot parameters */
900 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 903 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
901 904
902 #ifdef CONFIG_MXC_SPI 905 #ifdef CONFIG_MXC_SPI
903 setup_spi(); 906 setup_spi();
904 #endif 907 #endif
905 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 908 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
906 909
907 #ifdef CONFIG_USB_EHCI_MX6 910 #ifdef CONFIG_USB_EHCI_MX6
908 setup_usb(); 911 setup_usb();
909 #endif 912 #endif
910 913
911 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) 914 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
912 setup_epdc(); 915 setup_epdc();
913 #endif 916 #endif
914 917
915 #ifdef CONFIG_CMD_SATA 918 #ifdef CONFIG_CMD_SATA
916 setup_sata(); 919 setup_sata();
920 #endif
921
922 #ifdef CONFIG_FEC_MXC
923 setup_fec();
917 #endif 924 #endif
918 925
919 return 0; 926 return 0;
920 } 927 }
921 928
922 int power_init_board(void) 929 int power_init_board(void)
923 { 930 {
924 struct pmic *pfuze; 931 struct pmic *pfuze;
925 unsigned int reg; 932 unsigned int reg;
926 int ret; 933 int ret;
927 934
928 pfuze = pfuze_common_init(I2C_PMIC); 935 pfuze = pfuze_common_init(I2C_PMIC);
929 if (!pfuze) 936 if (!pfuze)
930 return -ENODEV; 937 return -ENODEV;
931 938
932 if (is_mx6dqp()) 939 if (is_mx6dqp())
933 ret = pfuze_mode_init(pfuze, APS_APS); 940 ret = pfuze_mode_init(pfuze, APS_APS);
934 else 941 else
935 ret = pfuze_mode_init(pfuze, APS_PFM); 942 ret = pfuze_mode_init(pfuze, APS_PFM);
936 943
937 if (ret < 0) 944 if (ret < 0)
938 return ret; 945 return ret;
939 946
940 /* Increase VGEN3 from 2.5 to 2.8V */ 947 /* Increase VGEN3 from 2.5 to 2.8V */
941 pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg); 948 pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg);
942 reg &= ~LDO_VOL_MASK; 949 reg &= ~LDO_VOL_MASK;
943 reg |= LDOB_2_80V; 950 reg |= LDOB_2_80V;
944 pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg); 951 pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);
945 952
946 /* Increase VGEN5 from 2.8 to 3V */ 953 /* Increase VGEN5 from 2.8 to 3V */
947 pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg); 954 pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
948 reg &= ~LDO_VOL_MASK; 955 reg &= ~LDO_VOL_MASK;
949 reg |= LDOB_3_00V; 956 reg |= LDOB_3_00V;
950 pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); 957 pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
951 958
952 if (is_mx6dqp()) { 959 if (is_mx6dqp()) {
953 /* set SW1C staby volatage 1.075V*/ 960 /* set SW1C staby volatage 1.075V*/
954 pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg); 961 pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
955 reg &= ~0x3f; 962 reg &= ~0x3f;
956 reg |= 0x1f; 963 reg |= 0x1f;
957 pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); 964 pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
958 965
959 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ 966 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
960 pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg); 967 pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
961 reg &= ~0xc0; 968 reg &= ~0xc0;
962 reg |= 0x40; 969 reg |= 0x40;
963 pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); 970 pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
964 971
965 /* set SW2/VDDARM staby volatage 0.975V*/ 972 /* set SW2/VDDARM staby volatage 0.975V*/
966 pmic_reg_read(pfuze, PFUZE100_SW2STBY, &reg); 973 pmic_reg_read(pfuze, PFUZE100_SW2STBY, &reg);
967 reg &= ~0x3f; 974 reg &= ~0x3f;
968 reg |= 0x17; 975 reg |= 0x17;
969 pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg); 976 pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg);
970 977
971 /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ 978 /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
972 pmic_reg_read(pfuze, PFUZE100_SW2CONF, &reg); 979 pmic_reg_read(pfuze, PFUZE100_SW2CONF, &reg);
973 reg &= ~0xc0; 980 reg &= ~0xc0;
974 reg |= 0x40; 981 reg |= 0x40;
975 pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg); 982 pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg);
976 } else { 983 } else {
977 /* set SW1AB staby volatage 0.975V*/ 984 /* set SW1AB staby volatage 0.975V*/
978 pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg); 985 pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
979 reg &= ~0x3f; 986 reg &= ~0x3f;
980 reg |= 0x1b; 987 reg |= 0x1b;
981 pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); 988 pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
982 989
983 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ 990 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
984 pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg); 991 pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
985 reg &= ~0xc0; 992 reg &= ~0xc0;
986 reg |= 0x40; 993 reg |= 0x40;
987 pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); 994 pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
988 995
989 /* set SW1C staby volatage 0.975V*/ 996 /* set SW1C staby volatage 0.975V*/
990 pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg); 997 pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
991 reg &= ~0x3f; 998 reg &= ~0x3f;
992 reg |= 0x1b; 999 reg |= 0x1b;
993 pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); 1000 pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
994 1001
995 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ 1002 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
996 pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg); 1003 pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
997 reg &= ~0xc0; 1004 reg &= ~0xc0;
998 reg |= 0x40; 1005 reg |= 0x40;
999 pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); 1006 pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
1000 } 1007 }
1001 1008
1002 return 0; 1009 return 0;
1003 } 1010 }
1004 1011
1005 #ifdef CONFIG_LDO_BYPASS_CHECK 1012 #ifdef CONFIG_LDO_BYPASS_CHECK
1006 void ldo_mode_set(int ldo_bypass) 1013 void ldo_mode_set(int ldo_bypass)
1007 { 1014 {
1008 unsigned int value; 1015 unsigned int value;
1009 int is_400M; 1016 int is_400M;
1010 unsigned char vddarm; 1017 unsigned char vddarm;
1011 struct pmic *p = pmic_get("PFUZE100"); 1018 struct pmic *p = pmic_get("PFUZE100");
1012 1019
1013 if (!p) { 1020 if (!p) {
1014 printf("No PMIC found!\n"); 1021 printf("No PMIC found!\n");
1015 return; 1022 return;
1016 } 1023 }
1017 1024
1018 /* increase VDDARM/VDDSOC to support 1.2G chip */ 1025 /* increase VDDARM/VDDSOC to support 1.2G chip */
1019 if (check_1_2G()) { 1026 if (check_1_2G()) {
1020 ldo_bypass = 0; /* ldo_enable on 1.2G chip */ 1027 ldo_bypass = 0; /* ldo_enable on 1.2G chip */
1021 printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); 1028 printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
1022 if (is_mx6dqp()) { 1029 if (is_mx6dqp()) {
1023 /* increase VDDARM to 1.425V */ 1030 /* increase VDDARM to 1.425V */
1024 pmic_reg_read(p, PFUZE100_SW2VOL, &value); 1031 pmic_reg_read(p, PFUZE100_SW2VOL, &value);
1025 value &= ~0x3f; 1032 value &= ~0x3f;
1026 value |= 0x29; 1033 value |= 0x29;
1027 pmic_reg_write(p, PFUZE100_SW2VOL, value); 1034 pmic_reg_write(p, PFUZE100_SW2VOL, value);
1028 } else { 1035 } else {
1029 /* increase VDDARM to 1.425V */ 1036 /* increase VDDARM to 1.425V */
1030 pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); 1037 pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
1031 value &= ~0x3f; 1038 value &= ~0x3f;
1032 value |= 0x2d; 1039 value |= 0x2d;
1033 pmic_reg_write(p, PFUZE100_SW1ABVOL, value); 1040 pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
1034 } 1041 }
1035 /* increase VDDSOC to 1.425V */ 1042 /* increase VDDSOC to 1.425V */
1036 pmic_reg_read(p, PFUZE100_SW1CVOL, &value); 1043 pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
1037 value &= ~0x3f; 1044 value &= ~0x3f;
1038 value |= 0x2d; 1045 value |= 0x2d;
1039 pmic_reg_write(p, PFUZE100_SW1CVOL, value); 1046 pmic_reg_write(p, PFUZE100_SW1CVOL, value);
1040 } 1047 }
1041 /* switch to ldo_bypass mode , boot on 800Mhz */ 1048 /* switch to ldo_bypass mode , boot on 800Mhz */
1042 if (ldo_bypass) { 1049 if (ldo_bypass) {
1043 prep_anatop_bypass(); 1050 prep_anatop_bypass();
1044 if (is_mx6dqp()) { 1051 if (is_mx6dqp()) {
1045 /* decrease VDDARM for 400Mhz DQP:1.1V*/ 1052 /* decrease VDDARM for 400Mhz DQP:1.1V*/
1046 pmic_reg_read(p, PFUZE100_SW2VOL, &value); 1053 pmic_reg_read(p, PFUZE100_SW2VOL, &value);
1047 value &= ~0x3f; 1054 value &= ~0x3f;
1048 value |= 0x1c; 1055 value |= 0x1c;
1049 pmic_reg_write(p, PFUZE100_SW2VOL, value); 1056 pmic_reg_write(p, PFUZE100_SW2VOL, value);
1050 } else { 1057 } else {
1051 /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ 1058 /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
1052 pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); 1059 pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
1053 value &= ~0x3f; 1060 value &= ~0x3f;
1054 if (is_cpu_type(MXC_CPU_MX6DL)) 1061 if (is_cpu_type(MXC_CPU_MX6DL))
1055 value |= 0x27; 1062 value |= 0x27;
1056 else 1063 else
1057 value |= 0x20; 1064 value |= 0x20;
1058 1065
1059 pmic_reg_write(p, PFUZE100_SW1ABVOL, value); 1066 pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
1060 } 1067 }
1061 /* increase VDDSOC to 1.3V */ 1068 /* increase VDDSOC to 1.3V */
1062 pmic_reg_read(p, PFUZE100_SW1CVOL, &value); 1069 pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
1063 value &= ~0x3f; 1070 value &= ~0x3f;
1064 value |= 0x28; 1071 value |= 0x28;
1065 pmic_reg_write(p, PFUZE100_SW1CVOL, value); 1072 pmic_reg_write(p, PFUZE100_SW1CVOL, value);
1066 1073
1067 /* 1074 /*
1068 * MX6Q/DQP: 1075 * MX6Q/DQP:
1069 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M 1076 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
1070 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M 1077 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
1071 * MX6DL: 1078 * MX6DL:
1072 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M 1079 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
1073 * VDDARM:1.075V@400M; VDDSOC:1.175V@400M 1080 * VDDARM:1.075V@400M; VDDSOC:1.175V@400M
1074 */ 1081 */
1075 is_400M = set_anatop_bypass(2); 1082 is_400M = set_anatop_bypass(2);
1076 if (is_mx6dqp()) { 1083 if (is_mx6dqp()) {
1077 pmic_reg_read(p, PFUZE100_SW2VOL, &value); 1084 pmic_reg_read(p, PFUZE100_SW2VOL, &value);
1078 value &= ~0x3f; 1085 value &= ~0x3f;
1079 if (is_400M) 1086 if (is_400M)
1080 value |= 0x17; 1087 value |= 0x17;
1081 else 1088 else
1082 value |= 0x1e; 1089 value |= 0x1e;
1083 pmic_reg_write(p, PFUZE100_SW2VOL, value); 1090 pmic_reg_write(p, PFUZE100_SW2VOL, value);
1084 } 1091 }
1085 1092
1086 if (is_400M) { 1093 if (is_400M) {
1087 if (is_cpu_type(MXC_CPU_MX6DL)) 1094 if (is_cpu_type(MXC_CPU_MX6DL))
1088 vddarm = 0x1f; 1095 vddarm = 0x1f;
1089 else 1096 else
1090 vddarm = 0x1b; 1097 vddarm = 0x1b;
1091 } else { 1098 } else {
1092 if (is_cpu_type(MXC_CPU_MX6DL)) 1099 if (is_cpu_type(MXC_CPU_MX6DL))
1093 vddarm = 0x23; 1100 vddarm = 0x23;
1094 else 1101 else
1095 vddarm = 0x22; 1102 vddarm = 0x22;
1096 } 1103 }
1097 pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); 1104 pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
1098 value &= ~0x3f; 1105 value &= ~0x3f;
1099 value |= vddarm; 1106 value |= vddarm;
1100 pmic_reg_write(p, PFUZE100_SW1ABVOL, value); 1107 pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
1101 1108
1102 /* decrease VDDSOC to 1.175V */ 1109 /* decrease VDDSOC to 1.175V */
1103 pmic_reg_read(p, PFUZE100_SW1CVOL, &value); 1110 pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
1104 value &= ~0x3f; 1111 value &= ~0x3f;
1105 value |= 0x23; 1112 value |= 0x23;
1106 pmic_reg_write(p, PFUZE100_SW1CVOL, value); 1113 pmic_reg_write(p, PFUZE100_SW1CVOL, value);
1107 1114
1108 finish_anatop_bypass(); 1115 finish_anatop_bypass();
1109 printf("switch to ldo_bypass mode!\n"); 1116 printf("switch to ldo_bypass mode!\n");
1110 } 1117 }
1111 } 1118 }
1112 #endif 1119 #endif
1113 1120
1114 #ifdef CONFIG_CMD_BMODE 1121 #ifdef CONFIG_CMD_BMODE
1115 static const struct boot_mode board_boot_modes[] = { 1122 static const struct boot_mode board_boot_modes[] = {
1116 /* 4 bit bus width */ 1123 /* 4 bit bus width */
1117 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 1124 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
1118 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 1125 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1119 /* 8 bit bus width */ 1126 /* 8 bit bus width */
1120 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, 1127 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
1121 {NULL, 0}, 1128 {NULL, 0},
1122 }; 1129 };
1123 #endif 1130 #endif
1124 1131
1125 int board_late_init(void) 1132 int board_late_init(void)
1126 { 1133 {
1127 #ifdef CONFIG_CMD_BMODE 1134 #ifdef CONFIG_CMD_BMODE
1128 add_board_boot_modes(board_boot_modes); 1135 add_board_boot_modes(board_boot_modes);
1129 #endif 1136 #endif
1130 1137
1131 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 1138 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
1132 setenv("board_name", "SABRESD"); 1139 setenv("board_name", "SABRESD");
1133 1140
1134 if (is_mx6dqp()) 1141 if (is_mx6dqp())
1135 setenv("board_rev", "MX6QP"); 1142 setenv("board_rev", "MX6QP");
1136 else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 1143 else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
1137 setenv("board_rev", "MX6Q"); 1144 setenv("board_rev", "MX6Q");
1138 else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) 1145 else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
1139 setenv("board_rev", "MX6DL"); 1146 setenv("board_rev", "MX6DL");
1140 #endif 1147 #endif
1141 1148
1142 #ifdef CONFIG_ENV_IS_IN_MMC 1149 #ifdef CONFIG_ENV_IS_IN_MMC
1143 board_late_mmc_env_init(); 1150 board_late_mmc_env_init();
1144 #endif 1151 #endif
1145 1152
1146 return 0; 1153 return 0;
1147 } 1154 }
1148 1155
1149 int checkboard(void) 1156 int checkboard(void)
1150 { 1157 {
1151 puts("Board: MX6-SabreSD\n"); 1158 puts("Board: MX6-SabreSD\n");
1152 return 0; 1159 return 0;
1153 } 1160 }
1154 1161
1155 #ifdef CONFIG_FSL_FASTBOOT 1162 #ifdef CONFIG_FSL_FASTBOOT
1156 1163
1157 void board_fastboot_setup(void) 1164 void board_fastboot_setup(void)
1158 { 1165 {
1159 switch (get_boot_device()) { 1166 switch (get_boot_device()) {
1160 #if defined(CONFIG_FASTBOOT_STORAGE_SATA) 1167 #if defined(CONFIG_FASTBOOT_STORAGE_SATA)
1161 case SATA_BOOT: 1168 case SATA_BOOT:
1162 if (!getenv("fastboot_dev")) 1169 if (!getenv("fastboot_dev"))
1163 setenv("fastboot_dev", "sata"); 1170 setenv("fastboot_dev", "sata");
1164 if (!getenv("bootcmd")) 1171 if (!getenv("bootcmd"))
1165 setenv("bootcmd", "boota sata"); 1172 setenv("bootcmd", "boota sata");
1166 break; 1173 break;
1167 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ 1174 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
1168 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 1175 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
1169 case SD2_BOOT: 1176 case SD2_BOOT:
1170 case MMC2_BOOT: 1177 case MMC2_BOOT:
1171 if (!getenv("fastboot_dev")) 1178 if (!getenv("fastboot_dev"))
1172 setenv("fastboot_dev", "mmc0"); 1179 setenv("fastboot_dev", "mmc0");
1173 if (!getenv("bootcmd")) 1180 if (!getenv("bootcmd"))
1174 setenv("bootcmd", "boota mmc0"); 1181 setenv("bootcmd", "boota mmc0");
1175 break; 1182 break;
1176 case SD3_BOOT: 1183 case SD3_BOOT:
1177 case MMC3_BOOT: 1184 case MMC3_BOOT:
1178 if (!getenv("fastboot_dev")) 1185 if (!getenv("fastboot_dev"))
1179 setenv("fastboot_dev", "mmc1"); 1186 setenv("fastboot_dev", "mmc1");
1180 if (!getenv("bootcmd")) 1187 if (!getenv("bootcmd"))
1181 setenv("bootcmd", "boota mmc1"); 1188 setenv("bootcmd", "boota mmc1");
1182 break; 1189 break;
1183 case MMC4_BOOT: 1190 case MMC4_BOOT:
1184 if (!getenv("fastboot_dev")) 1191 if (!getenv("fastboot_dev"))
1185 setenv("fastboot_dev", "mmc2"); 1192 setenv("fastboot_dev", "mmc2");
1186 if (!getenv("bootcmd")) 1193 if (!getenv("bootcmd"))
1187 setenv("bootcmd", "boota mmc2"); 1194 setenv("bootcmd", "boota mmc2");
1188 break; 1195 break;
1189 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1196 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1190 default: 1197 default:
1191 printf("unsupported boot devices\n"); 1198 printf("unsupported boot devices\n");
1192 break; 1199 break;
1193 } 1200 }
1194 1201
1195 } 1202 }
1196 1203
1197 #ifdef CONFIG_ANDROID_RECOVERY 1204 #ifdef CONFIG_ANDROID_RECOVERY
1198 1205
1199 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5) 1206 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
1200 iomux_v3_cfg_t const recovery_key_pads[] = { 1207 iomux_v3_cfg_t const recovery_key_pads[] = {
1201 (MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 1208 (MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
1202 }; 1209 };
1203 1210
1204 int check_recovery_cmd_file(void) 1211 int check_recovery_cmd_file(void)
1205 { 1212 {
1206 int button_pressed = 0; 1213 int button_pressed = 0;
1207 int recovery_mode = 0; 1214 int recovery_mode = 0;
1208 1215
1209 recovery_mode = recovery_check_and_clean_flag(); 1216 recovery_mode = recovery_check_and_clean_flag();
1210 1217
1211 /* Check Recovery Combo Button press or not. */ 1218 /* Check Recovery Combo Button press or not. */
1212 imx_iomux_v3_setup_multiple_pads(recovery_key_pads, 1219 imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
1213 ARRAY_SIZE(recovery_key_pads)); 1220 ARRAY_SIZE(recovery_key_pads));
1214 1221
1215 gpio_direction_input(GPIO_VOL_DN_KEY); 1222 gpio_direction_input(GPIO_VOL_DN_KEY);
1216 1223
1217 if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ 1224 if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
1218 button_pressed = 1; 1225 button_pressed = 1;
1219 printf("Recovery key pressed\n"); 1226 printf("Recovery key pressed\n");
1220 } 1227 }
1221 1228
1222 return recovery_mode || button_pressed; 1229 return recovery_mode || button_pressed;
1223 } 1230 }
1224 1231
1225 void board_recovery_setup(void) 1232 void board_recovery_setup(void)
1226 { 1233 {
1227 int bootdev = get_boot_device(); 1234 int bootdev = get_boot_device();
1228 1235
1229 switch (bootdev) { 1236 switch (bootdev) {
1230 #if defined(CONFIG_FASTBOOT_STORAGE_SATA) 1237 #if defined(CONFIG_FASTBOOT_STORAGE_SATA)
1231 case SATA_BOOT: 1238 case SATA_BOOT:
1232 if (!getenv("bootcmd_android_recovery")) 1239 if (!getenv("bootcmd_android_recovery"))
1233 setenv("bootcmd_android_recovery", 1240 setenv("bootcmd_android_recovery",
1234 "boota sata recovery"); 1241 "boota sata recovery");
1235 break; 1242 break;
1236 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ 1243 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
1237 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 1244 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
1238 case SD2_BOOT: 1245 case SD2_BOOT:
1239 case MMC2_BOOT: 1246 case MMC2_BOOT:
1240 if (!getenv("bootcmd_android_recovery")) 1247 if (!getenv("bootcmd_android_recovery"))
1241 setenv("bootcmd_android_recovery", 1248 setenv("bootcmd_android_recovery",
1242 "boota mmc0 recovery"); 1249 "boota mmc0 recovery");
1243 break; 1250 break;
1244 case SD3_BOOT: 1251 case SD3_BOOT:
1245 case MMC3_BOOT: 1252 case MMC3_BOOT:
1246 if (!getenv("bootcmd_android_recovery")) 1253 if (!getenv("bootcmd_android_recovery"))
1247 setenv("bootcmd_android_recovery", 1254 setenv("bootcmd_android_recovery",
1248 "boota mmc1 recovery"); 1255 "boota mmc1 recovery");
1249 break; 1256 break;
1250 case MMC4_BOOT: 1257 case MMC4_BOOT:
1251 if (!getenv("bootcmd_android_recovery")) 1258 if (!getenv("bootcmd_android_recovery"))
1252 setenv("bootcmd_android_recovery", 1259 setenv("bootcmd_android_recovery",
1253 "boota mmc2 recovery"); 1260 "boota mmc2 recovery");
1254 break; 1261 break;
1255 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 1262 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
1256 default: 1263 default:
1257 printf("Unsupported bootup device for recovery: dev: %d\n", 1264 printf("Unsupported bootup device for recovery: dev: %d\n",
1258 bootdev); 1265 bootdev);
1259 return; 1266 return;
1260 } 1267 }
1261 1268
1262 printf("setup env for recovery..\n"); 1269 printf("setup env for recovery..\n");
1263 setenv("bootcmd", "run bootcmd_android_recovery"); 1270 setenv("bootcmd", "run bootcmd_android_recovery");
1264 } 1271 }
1265 1272
1266 #endif /*CONFIG_ANDROID_RECOVERY*/ 1273 #endif /*CONFIG_ANDROID_RECOVERY*/
1267 1274
1268 #endif /*CONFIG_FSL_FASTBOOT*/ 1275 #endif /*CONFIG_FSL_FASTBOOT*/
1269 1276
1270 1277
1271 #ifdef CONFIG_SPL_BUILD 1278 #ifdef CONFIG_SPL_BUILD
1272 #include <spl.h> 1279 #include <spl.h>
1273 #include <libfdt.h> 1280 #include <libfdt.h>
1274 1281
1275 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 1282 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
1276 .dram_sdclk_0 = 0x00020030, 1283 .dram_sdclk_0 = 0x00020030,
1277 .dram_sdclk_1 = 0x00020030, 1284 .dram_sdclk_1 = 0x00020030,
1278 .dram_cas = 0x00020030, 1285 .dram_cas = 0x00020030,
1279 .dram_ras = 0x00020030, 1286 .dram_ras = 0x00020030,
1280 .dram_reset = 0x00020030, 1287 .dram_reset = 0x00020030,
1281 .dram_sdcke0 = 0x00003000, 1288 .dram_sdcke0 = 0x00003000,
1282 .dram_sdcke1 = 0x00003000, 1289 .dram_sdcke1 = 0x00003000,
1283 .dram_sdba2 = 0x00000000, 1290 .dram_sdba2 = 0x00000000,
1284 .dram_sdodt0 = 0x00003030, 1291 .dram_sdodt0 = 0x00003030,
1285 .dram_sdodt1 = 0x00003030, 1292 .dram_sdodt1 = 0x00003030,
1286 .dram_sdqs0 = 0x00000030, 1293 .dram_sdqs0 = 0x00000030,
1287 .dram_sdqs1 = 0x00000030, 1294 .dram_sdqs1 = 0x00000030,
1288 .dram_sdqs2 = 0x00000030, 1295 .dram_sdqs2 = 0x00000030,
1289 .dram_sdqs3 = 0x00000030, 1296 .dram_sdqs3 = 0x00000030,
1290 .dram_sdqs4 = 0x00000030, 1297 .dram_sdqs4 = 0x00000030,
1291 .dram_sdqs5 = 0x00000030, 1298 .dram_sdqs5 = 0x00000030,
1292 .dram_sdqs6 = 0x00000030, 1299 .dram_sdqs6 = 0x00000030,
1293 .dram_sdqs7 = 0x00000030, 1300 .dram_sdqs7 = 0x00000030,
1294 .dram_dqm0 = 0x00020030, 1301 .dram_dqm0 = 0x00020030,
1295 .dram_dqm1 = 0x00020030, 1302 .dram_dqm1 = 0x00020030,
1296 .dram_dqm2 = 0x00020030, 1303 .dram_dqm2 = 0x00020030,
1297 .dram_dqm3 = 0x00020030, 1304 .dram_dqm3 = 0x00020030,
1298 .dram_dqm4 = 0x00020030, 1305 .dram_dqm4 = 0x00020030,
1299 .dram_dqm5 = 0x00020030, 1306 .dram_dqm5 = 0x00020030,
1300 .dram_dqm6 = 0x00020030, 1307 .dram_dqm6 = 0x00020030,
1301 .dram_dqm7 = 0x00020030, 1308 .dram_dqm7 = 0x00020030,
1302 }; 1309 };
1303 1310
1304 const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = { 1311 const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
1305 .dram_sdclk_0 = 0x00000030, 1312 .dram_sdclk_0 = 0x00000030,
1306 .dram_sdclk_1 = 0x00000030, 1313 .dram_sdclk_1 = 0x00000030,
1307 .dram_cas = 0x00000030, 1314 .dram_cas = 0x00000030,
1308 .dram_ras = 0x00000030, 1315 .dram_ras = 0x00000030,
1309 .dram_reset = 0x00000030, 1316 .dram_reset = 0x00000030,
1310 .dram_sdcke0 = 0x00003000, 1317 .dram_sdcke0 = 0x00003000,
1311 .dram_sdcke1 = 0x00003000, 1318 .dram_sdcke1 = 0x00003000,
1312 .dram_sdba2 = 0x00000000, 1319 .dram_sdba2 = 0x00000000,
1313 .dram_sdodt0 = 0x00003030, 1320 .dram_sdodt0 = 0x00003030,
1314 .dram_sdodt1 = 0x00003030, 1321 .dram_sdodt1 = 0x00003030,
1315 .dram_sdqs0 = 0x00000030, 1322 .dram_sdqs0 = 0x00000030,
1316 .dram_sdqs1 = 0x00000030, 1323 .dram_sdqs1 = 0x00000030,
1317 .dram_sdqs2 = 0x00000030, 1324 .dram_sdqs2 = 0x00000030,
1318 .dram_sdqs3 = 0x00000030, 1325 .dram_sdqs3 = 0x00000030,
1319 .dram_sdqs4 = 0x00000030, 1326 .dram_sdqs4 = 0x00000030,
1320 .dram_sdqs5 = 0x00000030, 1327 .dram_sdqs5 = 0x00000030,
1321 .dram_sdqs6 = 0x00000030, 1328 .dram_sdqs6 = 0x00000030,
1322 .dram_sdqs7 = 0x00000030, 1329 .dram_sdqs7 = 0x00000030,
1323 .dram_dqm0 = 0x00000030, 1330 .dram_dqm0 = 0x00000030,
1324 .dram_dqm1 = 0x00000030, 1331 .dram_dqm1 = 0x00000030,
1325 .dram_dqm2 = 0x00000030, 1332 .dram_dqm2 = 0x00000030,
1326 .dram_dqm3 = 0x00000030, 1333 .dram_dqm3 = 0x00000030,
1327 .dram_dqm4 = 0x00000030, 1334 .dram_dqm4 = 0x00000030,
1328 .dram_dqm5 = 0x00000030, 1335 .dram_dqm5 = 0x00000030,
1329 .dram_dqm6 = 0x00000030, 1336 .dram_dqm6 = 0x00000030,
1330 .dram_dqm7 = 0x00000030, 1337 .dram_dqm7 = 0x00000030,
1331 }; 1338 };
1332 1339
1333 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 1340 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
1334 .grp_ddr_type = 0x000C0000, 1341 .grp_ddr_type = 0x000C0000,
1335 .grp_ddrmode_ctl = 0x00020000, 1342 .grp_ddrmode_ctl = 0x00020000,
1336 .grp_ddrpke = 0x00000000, 1343 .grp_ddrpke = 0x00000000,
1337 .grp_addds = 0x00000030, 1344 .grp_addds = 0x00000030,
1338 .grp_ctlds = 0x00000030, 1345 .grp_ctlds = 0x00000030,
1339 .grp_ddrmode = 0x00020000, 1346 .grp_ddrmode = 0x00020000,
1340 .grp_b0ds = 0x00000030, 1347 .grp_b0ds = 0x00000030,
1341 .grp_b1ds = 0x00000030, 1348 .grp_b1ds = 0x00000030,
1342 .grp_b2ds = 0x00000030, 1349 .grp_b2ds = 0x00000030,
1343 .grp_b3ds = 0x00000030, 1350 .grp_b3ds = 0x00000030,
1344 .grp_b4ds = 0x00000030, 1351 .grp_b4ds = 0x00000030,
1345 .grp_b5ds = 0x00000030, 1352 .grp_b5ds = 0x00000030,
1346 .grp_b6ds = 0x00000030, 1353 .grp_b6ds = 0x00000030,
1347 .grp_b7ds = 0x00000030, 1354 .grp_b7ds = 0x00000030,
1348 }; 1355 };
1349 1356
1350 const struct mx6_mmdc_calibration mx6_mmcd_calib = { 1357 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
1351 .p0_mpwldectrl0 = 0x001F001F, 1358 .p0_mpwldectrl0 = 0x001F001F,
1352 .p0_mpwldectrl1 = 0x001F001F, 1359 .p0_mpwldectrl1 = 0x001F001F,
1353 .p1_mpwldectrl0 = 0x00440044, 1360 .p1_mpwldectrl0 = 0x00440044,
1354 .p1_mpwldectrl1 = 0x00440044, 1361 .p1_mpwldectrl1 = 0x00440044,
1355 .p0_mpdgctrl0 = 0x434B0350, 1362 .p0_mpdgctrl0 = 0x434B0350,
1356 .p0_mpdgctrl1 = 0x034C0359, 1363 .p0_mpdgctrl1 = 0x034C0359,
1357 .p1_mpdgctrl0 = 0x434B0350, 1364 .p1_mpdgctrl0 = 0x434B0350,
1358 .p1_mpdgctrl1 = 0x03650348, 1365 .p1_mpdgctrl1 = 0x03650348,
1359 .p0_mprddlctl = 0x4436383B, 1366 .p0_mprddlctl = 0x4436383B,
1360 .p1_mprddlctl = 0x39393341, 1367 .p1_mprddlctl = 0x39393341,
1361 .p0_mpwrdlctl = 0x35373933, 1368 .p0_mpwrdlctl = 0x35373933,
1362 .p1_mpwrdlctl = 0x48254A36, 1369 .p1_mpwrdlctl = 0x48254A36,
1363 }; 1370 };
1364 1371
1365 const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = { 1372 const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
1366 .p0_mpwldectrl0 = 0x001B001E, 1373 .p0_mpwldectrl0 = 0x001B001E,
1367 .p0_mpwldectrl1 = 0x002E0029, 1374 .p0_mpwldectrl1 = 0x002E0029,
1368 .p1_mpwldectrl0 = 0x001B002A, 1375 .p1_mpwldectrl0 = 0x001B002A,
1369 .p1_mpwldectrl1 = 0x0019002C, 1376 .p1_mpwldectrl1 = 0x0019002C,
1370 .p0_mpdgctrl0 = 0x43240334, 1377 .p0_mpdgctrl0 = 0x43240334,
1371 .p0_mpdgctrl1 = 0x0324031A, 1378 .p0_mpdgctrl1 = 0x0324031A,
1372 .p1_mpdgctrl0 = 0x43340344, 1379 .p1_mpdgctrl0 = 0x43340344,
1373 .p1_mpdgctrl1 = 0x03280276, 1380 .p1_mpdgctrl1 = 0x03280276,
1374 .p0_mprddlctl = 0x44383A3E, 1381 .p0_mprddlctl = 0x44383A3E,
1375 .p1_mprddlctl = 0x3C3C3846, 1382 .p1_mprddlctl = 0x3C3C3846,
1376 .p0_mpwrdlctl = 0x2E303230, 1383 .p0_mpwrdlctl = 0x2E303230,
1377 .p1_mpwrdlctl = 0x38283E34, 1384 .p1_mpwrdlctl = 0x38283E34,
1378 }; 1385 };
1379 1386
1380 /* MT41K128M16JT-125 */ 1387 /* MT41K128M16JT-125 */
1381 static struct mx6_ddr3_cfg mem_ddr = { 1388 static struct mx6_ddr3_cfg mem_ddr = {
1382 .mem_speed = 1600, 1389 .mem_speed = 1600,
1383 .density = 2, 1390 .density = 2,
1384 .width = 16, 1391 .width = 16,
1385 .banks = 8, 1392 .banks = 8,
1386 .rowaddr = 14, 1393 .rowaddr = 14,
1387 .coladdr = 10, 1394 .coladdr = 10,
1388 .pagesz = 2, 1395 .pagesz = 2,
1389 .trcd = 1375, 1396 .trcd = 1375,
1390 .trcmin = 4875, 1397 .trcmin = 4875,
1391 .trasmin = 3500, 1398 .trasmin = 3500,
1392 }; 1399 };
1393 1400
1394 static void ccgr_init(void) 1401 static void ccgr_init(void)
1395 { 1402 {
1396 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1403 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1397 1404
1398 writel(0x00C03F3F, &ccm->CCGR0); 1405 writel(0x00C03F3F, &ccm->CCGR0);
1399 writel(0x0030FC03, &ccm->CCGR1); 1406 writel(0x0030FC03, &ccm->CCGR1);
1400 writel(0x0FFFC000, &ccm->CCGR2); 1407 writel(0x0FFFC000, &ccm->CCGR2);
1401 writel(0x3FF00000, &ccm->CCGR3); 1408 writel(0x3FF00000, &ccm->CCGR3);
1402 writel(0x00FFF300, &ccm->CCGR4); 1409 writel(0x00FFF300, &ccm->CCGR4);
1403 writel(0x0F0000C3, &ccm->CCGR5); 1410 writel(0x0F0000C3, &ccm->CCGR5);
1404 writel(0x000003FF, &ccm->CCGR6); 1411 writel(0x000003FF, &ccm->CCGR6);
1405 } 1412 }
1406 1413
1407 static void gpr_init(void) 1414 static void gpr_init(void)
1408 { 1415 {
1409 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 1416 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
1410 1417
1411 /* enable AXI cache for VDOA/VPU/IPU */ 1418 /* enable AXI cache for VDOA/VPU/IPU */
1412 writel(0xF00000CF, &iomux->gpr[4]); 1419 writel(0xF00000CF, &iomux->gpr[4]);
1413 if (is_mx6dqp()) { 1420 if (is_mx6dqp()) {
1414 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ 1421 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
1415 writel(0x007F007F, &iomux->gpr[6]); 1422 writel(0x007F007F, &iomux->gpr[6]);
1416 writel(0x007F007F, &iomux->gpr[7]); 1423 writel(0x007F007F, &iomux->gpr[7]);
1417 } else { 1424 } else {
1418 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 1425 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
1419 writel(0x007F007F, &iomux->gpr[6]); 1426 writel(0x007F007F, &iomux->gpr[6]);
1420 writel(0x007F007F, &iomux->gpr[7]); 1427 writel(0x007F007F, &iomux->gpr[7]);
1421 } 1428 }
1422 } 1429 }
1423 1430
1424 /* 1431 /*
1425 * This section requires the differentiation between iMX6 Sabre boards, but 1432 * This section requires the differentiation between iMX6 Sabre boards, but
1426 * for now, it will configure only for the mx6q variant. 1433 * for now, it will configure only for the mx6q variant.
1427 */ 1434 */
1428 static void spl_dram_init(void) 1435 static void spl_dram_init(void)
1429 { 1436 {
1430 struct mx6_ddr_sysinfo sysinfo = { 1437 struct mx6_ddr_sysinfo sysinfo = {
1431 /* width of data bus:0=16,1=32,2=64 */ 1438 /* width of data bus:0=16,1=32,2=64 */
1432 .dsize = 2, 1439 .dsize = 2,
1433 /* config for full 4GB range so that get_mem_size() works */ 1440 /* config for full 4GB range so that get_mem_size() works */
1434 .cs_density = 32, /* 32Gb per CS */ 1441 .cs_density = 32, /* 32Gb per CS */
1435 /* single chip select */ 1442 /* single chip select */
1436 .ncs = 1, 1443 .ncs = 1,
1437 .cs1_mirror = 0, 1444 .cs1_mirror = 0,
1438 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 1445 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
1439 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 1446 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
1440 .walat = 1, /* Write additional latency */ 1447 .walat = 1, /* Write additional latency */
1441 .ralat = 5, /* Read additional latency */ 1448 .ralat = 5, /* Read additional latency */
1442 .mif3_mode = 3, /* Command prediction working mode */ 1449 .mif3_mode = 3, /* Command prediction working mode */
1443 .bi_on = 1, /* Bank interleaving enabled */ 1450 .bi_on = 1, /* Bank interleaving enabled */
1444 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 1451 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
1445 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 1452 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
1446 .ddr_type = DDR_TYPE_DDR3, 1453 .ddr_type = DDR_TYPE_DDR3,
1447 }; 1454 };
1448 1455
1449 if (is_mx6dqp()) { 1456 if (is_mx6dqp()) {
1450 mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs); 1457 mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
1451 mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr); 1458 mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
1452 } else { 1459 } else {
1453 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); 1460 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
1454 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); 1461 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
1455 } 1462 }
1456 } 1463 }
1457 1464
1458 void board_init_f(ulong dummy) 1465 void board_init_f(ulong dummy)
1459 { 1466 {
1460 /* setup AIPS and disable watchdog */ 1467 /* setup AIPS and disable watchdog */
1461 arch_cpu_init(); 1468 arch_cpu_init();
1462 1469
1463 ccgr_init(); 1470 ccgr_init();
1464 gpr_init(); 1471 gpr_init();
1465 1472
1466 /* iomux and setup of i2c */ 1473 /* iomux and setup of i2c */
1467 board_early_init_f(); 1474 board_early_init_f();
1468 1475
1469 /* setup GP timer */ 1476 /* setup GP timer */
1470 timer_init(); 1477 timer_init();
1471 1478
1472 /* UART clocks enabled and gd valid - init serial console */ 1479 /* UART clocks enabled and gd valid - init serial console */
1473 preloader_console_init(); 1480 preloader_console_init();
1474 1481
1475 /* DDR initialization */ 1482 /* DDR initialization */
1476 spl_dram_init(); 1483 spl_dram_init();
1477 1484
1478 /* Clear the BSS. */ 1485 /* Clear the BSS. */
1479 memset(__bss_start, 0, __bss_end - __bss_start); 1486 memset(__bss_start, 0, __bss_end - __bss_start);
1480 1487
1481 /* load/boot image from boot device */ 1488 /* load/boot image from boot device */
1482 board_init_r(NULL, 0); 1489 board_init_r(NULL, 0);
1483 } 1490 }
1484 #endif 1491 #endif
1485 1492