Commit fd8fbf7fa0b10199ac89cd13cae851149f51accb
1 parent
81f74e47fc
Exists in
smarc-rel_imx_4.1.15_2.0.0_ga
MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATA
We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before this changing, SATA read/write can't work after it. And we have to re-init SATA. The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing. This patch is an work around that moves the ENET clock setting (enable_fec_anatop_clock) from ethernet init to board_init which is prior than SATA initialization. So there is no PLL6 change after SATA init. Signed-off-by: Ye Li <ye.li@nxp.com>
Showing 2 changed files with 14 additions and 4 deletions Side-by-side Diff
board/freescale/mx6qsabreauto/mx6qsabreauto.c
| ... | ... | @@ -476,13 +476,11 @@ |
| 476 | 476 | ret = enable_fec_anatop_clock(0, ENET_125MHZ); |
| 477 | 477 | if (ret) |
| 478 | 478 | printf("Error fec anatop clock settings!\n"); |
| 479 | - | |
| 480 | - setup_iomux_enet(); | |
| 481 | 479 | } |
| 482 | 480 | |
| 483 | 481 | int board_eth_init(bd_t *bis) |
| 484 | 482 | { |
| 485 | - setup_fec(); | |
| 483 | + setup_iomux_enet(); | |
| 486 | 484 | |
| 487 | 485 | return cpu_eth_init(bis); |
| 488 | 486 | } |
| ... | ... | @@ -724,6 +722,11 @@ |
| 724 | 722 | #ifdef CONFIG_SYS_USE_EIMNOR |
| 725 | 723 | setup_iomux_eimnor(); |
| 726 | 724 | #endif |
| 725 | + | |
| 726 | +#ifdef CONFIG_FEC_MXC | |
| 727 | + setup_fec(); | |
| 728 | +#endif | |
| 729 | + | |
| 727 | 730 | return 0; |
| 728 | 731 | } |
| 729 | 732 |
board/freescale/mx6sabresd/mx6sabresd.c
| ... | ... | @@ -803,7 +803,7 @@ |
| 803 | 803 | return 1; |
| 804 | 804 | } |
| 805 | 805 | |
| 806 | -int board_eth_init(bd_t *bis) | |
| 806 | +static void setup_fec(void) | |
| 807 | 807 | { |
| 808 | 808 | if (is_mx6dqp()) { |
| 809 | 809 | int ret; |
| 810 | 810 | |
| ... | ... | @@ -814,7 +814,10 @@ |
| 814 | 814 | if (ret) |
| 815 | 815 | printf("Error fec anatop clock settings!\n"); |
| 816 | 816 | } |
| 817 | +} | |
| 817 | 818 | |
| 819 | +int board_eth_init(bd_t *bis) | |
| 820 | +{ | |
| 818 | 821 | setup_iomux_enet(); |
| 819 | 822 | setup_pcie(); |
| 820 | 823 | |
| ... | ... | @@ -914,6 +917,10 @@ |
| 914 | 917 | |
| 915 | 918 | #ifdef CONFIG_CMD_SATA |
| 916 | 919 | setup_sata(); |
| 920 | +#endif | |
| 921 | + | |
| 922 | +#ifdef CONFIG_FEC_MXC | |
| 923 | + setup_fec(); | |
| 917 | 924 | #endif |
| 918 | 925 | |
| 919 | 926 | return 0; |
