Commit fd93c20f68ba7b86d2f45befa9235aaa6411e822
Committed by
Lokesh Vutla
Lokesh Vutla
1 parent
910eed8ee6
Exists in
v2015.07-smarct4x
and in
3 other branches
ARM: OMAP5/AM43xx: remove enabling USB clocks from enable_basic_clocks()
Now that we have separate function to enable USB clocks, remove enabling USB clocks from enable_basic_clocks(). Now board_usb_init() should take care to invoke enable_usb_clocks() for enabling USB clocks. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Showing 2 changed files with 0 additions and 42 deletions Side-by-side Diff
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
| ... | ... | @@ -111,21 +111,9 @@ |
| 111 | 111 | &cmper->emifclkctrl, |
| 112 | 112 | &cmper->otfaemifclkctrl, |
| 113 | 113 | &cmper->qspiclkctrl, |
| 114 | - &cmper->usb0clkctrl, | |
| 115 | - &cmper->usbphyocp2scp0clkctrl, | |
| 116 | - &cmper->usb1clkctrl, | |
| 117 | - &cmper->usbphyocp2scp1clkctrl, | |
| 118 | 114 | 0 |
| 119 | 115 | }; |
| 120 | 116 | |
| 121 | - setbits_le32(&cmper->usb0clkctrl, | |
| 122 | - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); | |
| 123 | - setbits_le32(&cmwkup->usbphy0clkctrl, | |
| 124 | - USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); | |
| 125 | - setbits_le32(&cmper->usb1clkctrl, | |
| 126 | - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); | |
| 127 | - setbits_le32(&cmwkup->usbphy1clkctrl, | |
| 128 | - USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); | |
| 129 | 117 | do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); |
| 130 | 118 | |
| 131 | 119 | /* Select the Master osc clk as Timer2 clock source */ |
arch/arm/cpu/armv7/omap5/hw_data.c
| ... | ... | @@ -460,13 +460,6 @@ |
| 460 | 460 | (*prcm)->cm_l4per_gpio6_clkctrl, |
| 461 | 461 | (*prcm)->cm_l4per_gpio7_clkctrl, |
| 462 | 462 | (*prcm)->cm_l4per_gpio8_clkctrl, |
| 463 | -#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) | |
| 464 | - (*prcm)->cm_l3init_ocp2scp1_clkctrl, | |
| 465 | - (*prcm)->cm_l3init_usb_otg_ss1_clkctrl, | |
| 466 | -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) | |
| 467 | - (*prcm)->cm_l3init_usb_otg_ss2_clkctrl, | |
| 468 | -#endif | |
| 469 | -#endif | |
| 470 | 463 | 0 |
| 471 | 464 | }; |
| 472 | 465 | |
| ... | ... | @@ -497,29 +490,6 @@ |
| 497 | 490 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 498 | 491 | setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 499 | 492 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 500 | - | |
| 501 | -#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) | |
| 502 | - /* Enable 960 MHz clock for dwc3 */ | |
| 503 | - setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, | |
| 504 | - OPTFCLKEN_REFCLK960M); | |
| 505 | - | |
| 506 | - /* Enable 32 KHz clock for dwc3 */ | |
| 507 | - setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, | |
| 508 | - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
| 509 | -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) | |
| 510 | - /* Enable 960 MHz clock for dwc3 */ | |
| 511 | - setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, | |
| 512 | - OPTFCLKEN_REFCLK960M); | |
| 513 | - | |
| 514 | - /* Enable 32 KHz clock for dwc3 */ | |
| 515 | - setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, | |
| 516 | - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
| 517 | - | |
| 518 | - /* Enable 60 MHz clock for USB2PHY2 */ | |
| 519 | - setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, | |
| 520 | - L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); | |
| 521 | -#endif | |
| 522 | -#endif | |
| 523 | 493 | |
| 524 | 494 | /* Set the correct clock dividers for mmc */ |
| 525 | 495 | setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, |