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Commit ff255e836a3a6cd52bd51a192af96ac5f224dc22

Authored by Bo Shen
Committed by Andreas Bießmann
1 parent d85e8914b3
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: atmel: at91sam9n12ek: enable spl support 

Enable SPL support for at91sam9n12ek boards, now it supports
boot up from NAND flash, serial flash.

Signed-off-by: Bo Shen <voice.shen@atmel.com>

Showing 9 changed files with 138 additions and 5 deletions Inline Diff

arch/arm/mach-at91/Kconfig
Diff comments   View file @ ff255e8
1 if ARCH_AT91 1 if ARCH_AT91
2 2
3 choice 3 choice
4 prompt "Atmel AT91 board select" 4 prompt "Atmel AT91 board select"
5 5
6 config TARGET_AT91RM9200EK 6 config TARGET_AT91RM9200EK
7 bool "Atmel AT91RM9200 evaluation kit" 7 bool "Atmel AT91RM9200 evaluation kit"
8 select CPU_ARM920T 8 select CPU_ARM920T
9 9
10 config TARGET_EB_CPUX9K2 10 config TARGET_EB_CPUX9K2
11 bool "Support eb_cpux9k2" 11 bool "Support eb_cpux9k2"
12 select CPU_ARM920T 12 select CPU_ARM920T
13 13
14 config TARGET_CPUAT91 14 config TARGET_CPUAT91
15 bool "Support cpuat91" 15 bool "Support cpuat91"
16 select CPU_ARM920T 16 select CPU_ARM920T
17 17
18 config TARGET_AT91SAM9260EK 18 config TARGET_AT91SAM9260EK
19 bool "Atmel at91sam9260 reference board" 19 bool "Atmel at91sam9260 reference board"
20 select CPU_ARM926EJS 20 select CPU_ARM926EJS
21 21
22 config TARGET_ETHERNUT5 22 config TARGET_ETHERNUT5
23 bool "Ethernut5 board" 23 bool "Ethernut5 board"
24 select CPU_ARM926EJS 24 select CPU_ARM926EJS
25 25
26 config TARGET_TNY_A9260 26 config TARGET_TNY_A9260
27 bool "Caloa TNY A9260 board" 27 bool "Caloa TNY A9260 board"
28 select CPU_ARM926EJS 28 select CPU_ARM926EJS
29 29
30 config TARGET_SNAPPER9260 30 config TARGET_SNAPPER9260
31 bool "Support snapper9260" 31 bool "Support snapper9260"
32 select CPU_ARM926EJS 32 select CPU_ARM926EJS
33 33
34 config TARGET_AFEB9260 34 config TARGET_AFEB9260
35 bool "Support afeb9260" 35 bool "Support afeb9260"
36 select CPU_ARM926EJS 36 select CPU_ARM926EJS
37 37
38 config TARGET_AT91SAM9261EK 38 config TARGET_AT91SAM9261EK
39 bool "Atmel at91sam9261 reference board" 39 bool "Atmel at91sam9261 reference board"
40 select CPU_ARM926EJS 40 select CPU_ARM926EJS
41 41
42 config TARGET_PM9261 42 config TARGET_PM9261
43 bool "Ronetix pm9261 board" 43 bool "Ronetix pm9261 board"
44 select CPU_ARM926EJS 44 select CPU_ARM926EJS
45 45
46 config TARGET_AT91SAM9263EK 46 config TARGET_AT91SAM9263EK
47 bool "Atmel at91sam9263 reference board" 47 bool "Atmel at91sam9263 reference board"
48 select CPU_ARM926EJS 48 select CPU_ARM926EJS
49 49
50 config TARGET_USB_A9263 50 config TARGET_USB_A9263
51 bool "Caloa USB A9260 board" 51 bool "Caloa USB A9260 board"
52 select CPU_ARM926EJS 52 select CPU_ARM926EJS
53 53
54 config TARGET_PM9263 54 config TARGET_PM9263
55 bool "Ronetix pm9263 board" 55 bool "Ronetix pm9263 board"
56 select CPU_ARM926EJS 56 select CPU_ARM926EJS
57 57
58 config TARGET_SBC35_A9G20 58 config TARGET_SBC35_A9G20
59 bool "Support sbc35_a9g20" 59 bool "Support sbc35_a9g20"
60 select CPU_ARM926EJS 60 select CPU_ARM926EJS
61 61
62 config TARGET_STAMP9G20 62 config TARGET_STAMP9G20
63 bool "Support stamp9g20" 63 bool "Support stamp9g20"
64 select CPU_ARM926EJS 64 select CPU_ARM926EJS
65 65
66 config TARGET_AT91SAM9M10G45EK 66 config TARGET_AT91SAM9M10G45EK
67 bool "Atmel AT91SAM9M10G45-EK board" 67 bool "Atmel AT91SAM9M10G45-EK board"
68 select CPU_ARM926EJS 68 select CPU_ARM926EJS
69 select SUPPORT_SPL 69 select SUPPORT_SPL
70 70
71 config TARGET_PM9G45 71 config TARGET_PM9G45
72 bool "Ronetix pm9g45 board" 72 bool "Ronetix pm9g45 board"
73 select CPU_ARM926EJS 73 select CPU_ARM926EJS
74 74
75 config TARGET_AT91SAM9N12EK 75 config TARGET_AT91SAM9N12EK
76 bool "Atmel AT91SAM9N12-EK board" 76 bool "Atmel AT91SAM9N12-EK board"
77 select CPU_ARM926EJS 77 select CPU_ARM926EJS
78 select SUPPORT_SPL
78 79
79 config TARGET_AT91SAM9RLEK 80 config TARGET_AT91SAM9RLEK
80 bool "Atmel at91sam9rl reference board" 81 bool "Atmel at91sam9rl reference board"
81 select CPU_ARM926EJS 82 select CPU_ARM926EJS
82 83
83 config TARGET_AT91SAM9X5EK 84 config TARGET_AT91SAM9X5EK
84 bool "Atmel AT91SAM9X5-EK board" 85 bool "Atmel AT91SAM9X5-EK board"
85 select CPU_ARM926EJS 86 select CPU_ARM926EJS
86 select SUPPORT_SPL 87 select SUPPORT_SPL
87 88
88 config TARGET_SAMA5D3_XPLAINED 89 config TARGET_SAMA5D3_XPLAINED
89 bool "SAMA5D3 Xplained board" 90 bool "SAMA5D3 Xplained board"
90 select CPU_V7 91 select CPU_V7
91 select SUPPORT_SPL 92 select SUPPORT_SPL
92 93
93 config TARGET_SAMA5D3XEK 94 config TARGET_SAMA5D3XEK
94 bool "SAMA5D3X-EK board" 95 bool "SAMA5D3X-EK board"
95 select CPU_V7 96 select CPU_V7
96 select SUPPORT_SPL 97 select SUPPORT_SPL
97 98
98 config TARGET_SAMA5D4_XPLAINED 99 config TARGET_SAMA5D4_XPLAINED
99 bool "SAMA5D4 Xplained board" 100 bool "SAMA5D4 Xplained board"
100 select CPU_V7 101 select CPU_V7
101 select SUPPORT_SPL 102 select SUPPORT_SPL
102 103
103 config TARGET_SAMA5D4EK 104 config TARGET_SAMA5D4EK
104 bool "SAMA5D4 Evaluation Kit" 105 bool "SAMA5D4 Evaluation Kit"
105 select CPU_V7 106 select CPU_V7
106 select SUPPORT_SPL 107 select SUPPORT_SPL
107 108
108 config TARGET_VL_MA2SC 109 config TARGET_VL_MA2SC
109 bool "Support vl_ma2sc" 110 bool "Support vl_ma2sc"
110 select CPU_ARM926EJS 111 select CPU_ARM926EJS
111 112
112 config TARGET_MEESC 113 config TARGET_MEESC
113 bool "Support meesc" 114 bool "Support meesc"
114 select CPU_ARM926EJS 115 select CPU_ARM926EJS
115 116
116 config TARGET_OTC570 117 config TARGET_OTC570
117 bool "Support otc570" 118 bool "Support otc570"
118 select CPU_ARM926EJS 119 select CPU_ARM926EJS
119 120
120 config TARGET_CPU9260 121 config TARGET_CPU9260
121 bool "Support cpu9260" 122 bool "Support cpu9260"
122 select CPU_ARM926EJS 123 select CPU_ARM926EJS
123 124
124 config TARGET_CORVUS 125 config TARGET_CORVUS
125 bool "Support corvus" 126 bool "Support corvus"
126 select CPU_ARM926EJS 127 select CPU_ARM926EJS
127 select SUPPORT_SPL 128 select SUPPORT_SPL
128 129
129 config TARGET_TAURUS 130 config TARGET_TAURUS
130 bool "Support taurus" 131 bool "Support taurus"
131 select CPU_ARM926EJS 132 select CPU_ARM926EJS
132 select SUPPORT_SPL 133 select SUPPORT_SPL
133 134
134 endchoice 135 endchoice
135 136
136 config SYS_SOC 137 config SYS_SOC
137 default "at91" 138 default "at91"
138 139
139 source "board/atmel/at91rm9200ek/Kconfig" 140 source "board/atmel/at91rm9200ek/Kconfig"
140 source "board/atmel/at91sam9260ek/Kconfig" 141 source "board/atmel/at91sam9260ek/Kconfig"
141 source "board/atmel/at91sam9261ek/Kconfig" 142 source "board/atmel/at91sam9261ek/Kconfig"
142 source "board/atmel/at91sam9263ek/Kconfig" 143 source "board/atmel/at91sam9263ek/Kconfig"
143 source "board/atmel/at91sam9m10g45ek/Kconfig" 144 source "board/atmel/at91sam9m10g45ek/Kconfig"
144 source "board/atmel/at91sam9n12ek/Kconfig" 145 source "board/atmel/at91sam9n12ek/Kconfig"
145 source "board/atmel/at91sam9rlek/Kconfig" 146 source "board/atmel/at91sam9rlek/Kconfig"
146 source "board/atmel/at91sam9x5ek/Kconfig" 147 source "board/atmel/at91sam9x5ek/Kconfig"
147 source "board/atmel/sama5d3_xplained/Kconfig" 148 source "board/atmel/sama5d3_xplained/Kconfig"
148 source "board/atmel/sama5d3xek/Kconfig" 149 source "board/atmel/sama5d3xek/Kconfig"
149 source "board/atmel/sama5d4_xplained/Kconfig" 150 source "board/atmel/sama5d4_xplained/Kconfig"
150 source "board/atmel/sama5d4ek/Kconfig" 151 source "board/atmel/sama5d4ek/Kconfig"
151 source "board/BuS/eb_cpux9k2/Kconfig" 152 source "board/BuS/eb_cpux9k2/Kconfig"
152 source "board/eukrea/cpuat91/Kconfig" 153 source "board/eukrea/cpuat91/Kconfig"
153 source "board/afeb9260/Kconfig" 154 source "board/afeb9260/Kconfig"
154 source "board/bluewater/snapper9260/Kconfig" 155 source "board/bluewater/snapper9260/Kconfig"
155 source "board/BuS/vl_ma2sc/Kconfig" 156 source "board/BuS/vl_ma2sc/Kconfig"
156 source "board/calao/sbc35_a9g20/Kconfig" 157 source "board/calao/sbc35_a9g20/Kconfig"
157 source "board/calao/tny_a9260/Kconfig" 158 source "board/calao/tny_a9260/Kconfig"
158 source "board/calao/usb_a9263/Kconfig" 159 source "board/calao/usb_a9263/Kconfig"
159 source "board/egnite/ethernut5/Kconfig" 160 source "board/egnite/ethernut5/Kconfig"
160 source "board/esd/meesc/Kconfig" 161 source "board/esd/meesc/Kconfig"
161 source "board/esd/otc570/Kconfig" 162 source "board/esd/otc570/Kconfig"
162 source "board/eukrea/cpu9260/Kconfig" 163 source "board/eukrea/cpu9260/Kconfig"
163 source "board/ronetix/pm9261/Kconfig" 164 source "board/ronetix/pm9261/Kconfig"
164 source "board/ronetix/pm9263/Kconfig" 165 source "board/ronetix/pm9263/Kconfig"
165 source "board/ronetix/pm9g45/Kconfig" 166 source "board/ronetix/pm9g45/Kconfig"
166 source "board/siemens/corvus/Kconfig" 167 source "board/siemens/corvus/Kconfig"
167 source "board/siemens/taurus/Kconfig" 168 source "board/siemens/taurus/Kconfig"
168 source "board/taskit/stamp9g20/Kconfig" 169 source "board/taskit/stamp9g20/Kconfig"
169 170
170 endif 171 endif
171 172
arch/arm/mach-at91/Makefile
Diff comments   View file @ ff255e8
1 obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o 1 obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
2 ifneq ($(CONFIG_SPL_BUILD),) 2 ifneq ($(CONFIG_SPL_BUILD),)
3 obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o 3 obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
4 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o 4 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
5 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
5 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o 6 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
6 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o 7 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
7 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o 8 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
8 obj-y += spl.o 9 obj-y += spl.o
9 endif 10 endif
10 11
11 obj-$(CONFIG_CPU_ARM920T) += arm920t/ 12 obj-$(CONFIG_CPU_ARM920T) += arm920t/
12 obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/ 13 obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/
13 obj-$(CONFIG_CPU_V7) += armv7/ 14 obj-$(CONFIG_CPU_V7) += armv7/
14 15
arch/arm/mach-at91/include/mach/at91_pmc.h
Diff comments   View file @ ff255e8
1 /* 1 /*
2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] 2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
6 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 6 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
7 * 7 *
8 * Power Management Controller (PMC) - System peripherals registers. 8 * Power Management Controller (PMC) - System peripherals registers.
9 * Based on AT91RM9200 datasheet revision E. 9 * Based on AT91RM9200 datasheet revision E.
10 * 10 *
11 * SPDX-License-Identifier: GPL-2.0+ 11 * SPDX-License-Identifier: GPL-2.0+
12 */ 12 */
13 13
14 #ifndef AT91_PMC_H 14 #ifndef AT91_PMC_H
15 #define AT91_PMC_H 15 #define AT91_PMC_H
16 16
17 #ifdef __ASSEMBLY__ 17 #ifdef __ASSEMBLY__
18 18
19 #define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20) 19 #define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
20 #define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28) 20 #define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
21 #define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c) 21 #define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
22 #define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30) 22 #define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
23 #define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68) 23 #define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
24 24
25 #else 25 #else
26 26
27 #include <asm/types.h> 27 #include <asm/types.h>
28 28
29 typedef struct at91_pmc { 29 typedef struct at91_pmc {
30 u32 scer; /* 0x00 System Clock Enable Register */ 30 u32 scer; /* 0x00 System Clock Enable Register */
31 u32 scdr; /* 0x04 System Clock Disable Register */ 31 u32 scdr; /* 0x04 System Clock Disable Register */
32 u32 scsr; /* 0x08 System Clock Status Register */ 32 u32 scsr; /* 0x08 System Clock Status Register */
33 u32 reserved0; 33 u32 reserved0;
34 u32 pcer; /* 0x10 Peripheral Clock Enable Register */ 34 u32 pcer; /* 0x10 Peripheral Clock Enable Register */
35 u32 pcdr; /* 0x14 Peripheral Clock Disable Register */ 35 u32 pcdr; /* 0x14 Peripheral Clock Disable Register */
36 u32 pcsr; /* 0x18 Peripheral Clock Status Register */ 36 u32 pcsr; /* 0x18 Peripheral Clock Status Register */
37 u32 uckr; /* 0x1C UTMI Clock Register */ 37 u32 uckr; /* 0x1C UTMI Clock Register */
38 u32 mor; /* 0x20 Main Oscilator Register */ 38 u32 mor; /* 0x20 Main Oscilator Register */
39 u32 mcfr; /* 0x24 Main Clock Frequency Register */ 39 u32 mcfr; /* 0x24 Main Clock Frequency Register */
40 u32 pllar; /* 0x28 PLL A Register */ 40 u32 pllar; /* 0x28 PLL A Register */
41 u32 pllbr; /* 0x2C PLL B Register */ 41 u32 pllbr; /* 0x2C PLL B Register */
42 u32 mckr; /* 0x30 Master Clock Register */ 42 u32 mckr; /* 0x30 Master Clock Register */
43 u32 reserved1; 43 u32 reserved1;
44 u32 usb; /* 0x38 USB Clock Register */ 44 u32 usb; /* 0x38 USB Clock Register */
45 u32 reserved2; 45 u32 reserved2;
46 u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */ 46 u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */
47 u32 reserved3[4]; 47 u32 reserved3[4];
48 u32 ier; /* 0x60 Interrupt Enable Register */ 48 u32 ier; /* 0x60 Interrupt Enable Register */
49 u32 idr; /* 0x64 Interrupt Disable Register */ 49 u32 idr; /* 0x64 Interrupt Disable Register */
50 u32 sr; /* 0x68 Status Register */ 50 u32 sr; /* 0x68 Status Register */
51 u32 imr; /* 0x6C Interrupt Mask Register */ 51 u32 imr; /* 0x6C Interrupt Mask Register */
52 u32 reserved4[4]; 52 u32 reserved4[4];
53 u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */ 53 u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */
54 u32 reserved5[21]; 54 u32 reserved5[21];
55 u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ 55 u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
56 u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ 56 u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
57 #ifdef CPU_HAS_PCR 57 #ifdef CPU_HAS_PCR
58 u32 reserved6[8]; 58 u32 reserved6[8];
59 u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */ 59 u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
60 u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */ 60 u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
61 u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */ 61 u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */
62 u32 pcr; /* 0x10c Periperial Control Register */ 62 u32 pcr; /* 0x10c Periperial Control Register */
63 u32 ocr; /* 0x110 Oscillator Calibration Register */ 63 u32 ocr; /* 0x110 Oscillator Calibration Register */
64 #else 64 #else
65 u32 reserved8[5]; 65 u32 reserved8[5];
66 #endif 66 #endif
67 } at91_pmc_t; 67 } at91_pmc_t;
68 68
69 #endif /* end not assembly */ 69 #endif /* end not assembly */
70 70
71 #define AT91_PMC_MOR_MOSCEN 0x01 71 #define AT91_PMC_MOR_MOSCEN 0x01
72 #define AT91_PMC_MOR_OSCBYPASS 0x02 72 #define AT91_PMC_MOR_OSCBYPASS 0x02
73 #define AT91_PMC_MOR_MOSCRCEN 0x08 73 #define AT91_PMC_MOR_MOSCRCEN 0x08
74 #define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) 74 #define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8)
75 #define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16) 75 #define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16)
76 #define AT91_PMC_MOR_MOSCSEL (1 << 24) 76 #define AT91_PMC_MOR_MOSCSEL (1 << 24)
77 77
78 #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) 78 #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
79 #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) 79 #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
80 #define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) 80 #define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
81 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) 81 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
82 #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) 82 #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
83 #else 83 #else
84 #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) 84 #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
85 #endif 85 #endif
86 #define AT91_PMC_PLLAR_29 0x20000000 86 #define AT91_PMC_PLLAR_29 0x20000000
87 #define AT91_PMC_PLLBR_USBDIV_1 0x00000000 87 #define AT91_PMC_PLLBR_USBDIV_1 0x00000000
88 #define AT91_PMC_PLLBR_USBDIV_2 0x10000000 88 #define AT91_PMC_PLLBR_USBDIV_2 0x10000000
89 #define AT91_PMC_PLLBR_USBDIV_4 0x20000000 89 #define AT91_PMC_PLLBR_USBDIV_4 0x20000000
90 90
91 #define AT91_PMC_MCFR_MAINRDY 0x00010000 91 #define AT91_PMC_MCFR_MAINRDY 0x00010000
92 #define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF 92 #define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF
93 93
94 #define AT91_PMC_MCKR_CSS_SLOW 0x00000000 94 #define AT91_PMC_MCKR_CSS_SLOW 0x00000000
95 #define AT91_PMC_MCKR_CSS_MAIN 0x00000001 95 #define AT91_PMC_MCKR_CSS_MAIN 0x00000001
96 #define AT91_PMC_MCKR_CSS_PLLA 0x00000002 96 #define AT91_PMC_MCKR_CSS_PLLA 0x00000002
97 #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 97 #define AT91_PMC_MCKR_CSS_PLLB 0x00000003
98 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 98 #define AT91_PMC_MCKR_CSS_MASK 0x00000003
99 99
100 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ 100 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
101 defined(CONFIG_AT91SAM9X5) 101 defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
102 #define AT91_PMC_MCKR_PRES_1 0x00000000 102 #define AT91_PMC_MCKR_PRES_1 0x00000000
103 #define AT91_PMC_MCKR_PRES_2 0x00000010 103 #define AT91_PMC_MCKR_PRES_2 0x00000010
104 #define AT91_PMC_MCKR_PRES_4 0x00000020 104 #define AT91_PMC_MCKR_PRES_4 0x00000020
105 #define AT91_PMC_MCKR_PRES_8 0x00000030 105 #define AT91_PMC_MCKR_PRES_8 0x00000030
106 #define AT91_PMC_MCKR_PRES_16 0x00000040 106 #define AT91_PMC_MCKR_PRES_16 0x00000040
107 #define AT91_PMC_MCKR_PRES_32 0x00000050 107 #define AT91_PMC_MCKR_PRES_32 0x00000050
108 #define AT91_PMC_MCKR_PRES_64 0x00000060 108 #define AT91_PMC_MCKR_PRES_64 0x00000060
109 #define AT91_PMC_MCKR_PRES_MASK 0x00000070 109 #define AT91_PMC_MCKR_PRES_MASK 0x00000070
110 #else 110 #else
111 #define AT91_PMC_MCKR_PRES_1 0x00000000 111 #define AT91_PMC_MCKR_PRES_1 0x00000000
112 #define AT91_PMC_MCKR_PRES_2 0x00000004 112 #define AT91_PMC_MCKR_PRES_2 0x00000004
113 #define AT91_PMC_MCKR_PRES_4 0x00000008 113 #define AT91_PMC_MCKR_PRES_4 0x00000008
114 #define AT91_PMC_MCKR_PRES_8 0x0000000C 114 #define AT91_PMC_MCKR_PRES_8 0x0000000C
115 #define AT91_PMC_MCKR_PRES_16 0x00000010 115 #define AT91_PMC_MCKR_PRES_16 0x00000010
116 #define AT91_PMC_MCKR_PRES_32 0x00000014 116 #define AT91_PMC_MCKR_PRES_32 0x00000014
117 #define AT91_PMC_MCKR_PRES_64 0x00000018 117 #define AT91_PMC_MCKR_PRES_64 0x00000018
118 #define AT91_PMC_MCKR_PRES_MASK 0x0000001C 118 #define AT91_PMC_MCKR_PRES_MASK 0x0000001C
119 #endif 119 #endif
120 120
121 #ifdef CONFIG_AT91RM9200 121 #ifdef CONFIG_AT91RM9200
122 #define AT91_PMC_MCKR_MDIV_1 0x00000000 122 #define AT91_PMC_MCKR_MDIV_1 0x00000000
123 #define AT91_PMC_MCKR_MDIV_2 0x00000100 123 #define AT91_PMC_MCKR_MDIV_2 0x00000100
124 #define AT91_PMC_MCKR_MDIV_3 0x00000200 124 #define AT91_PMC_MCKR_MDIV_3 0x00000200
125 #define AT91_PMC_MCKR_MDIV_4 0x00000300 125 #define AT91_PMC_MCKR_MDIV_4 0x00000300
126 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 126 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300
127 #else 127 #else
128 #define AT91_PMC_MCKR_MDIV_1 0x00000000 128 #define AT91_PMC_MCKR_MDIV_1 0x00000000
129 #define AT91_PMC_MCKR_MDIV_2 0x00000100 129 #define AT91_PMC_MCKR_MDIV_2 0x00000100
130 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ 130 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
131 defined(CONFIG_AT91SAM9X5) 131 defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
132 #define AT91_PMC_MCKR_MDIV_3 0x00000300 132 #define AT91_PMC_MCKR_MDIV_3 0x00000300
133 #endif 133 #endif
134 #define AT91_PMC_MCKR_MDIV_4 0x00000200 134 #define AT91_PMC_MCKR_MDIV_4 0x00000200
135 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 135 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300
136 #endif 136 #endif
137 137
138 #define AT91_PMC_MCKR_PLLADIV_MASK 0x00003000 138 #define AT91_PMC_MCKR_PLLADIV_MASK 0x00003000
139 #define AT91_PMC_MCKR_PLLADIV_1 0x00000000 139 #define AT91_PMC_MCKR_PLLADIV_1 0x00000000
140 #define AT91_PMC_MCKR_PLLADIV_2 0x00001000 140 #define AT91_PMC_MCKR_PLLADIV_2 0x00001000
141 141
142 #define AT91_PMC_MCKR_H32MXDIV 0x01000000 142 #define AT91_PMC_MCKR_H32MXDIV 0x01000000
143 143
144 #define AT91_PMC_IXR_MOSCS 0x00000001 144 #define AT91_PMC_IXR_MOSCS 0x00000001
145 #define AT91_PMC_IXR_LOCKA 0x00000002 145 #define AT91_PMC_IXR_LOCKA 0x00000002
146 #define AT91_PMC_IXR_LOCKB 0x00000004 146 #define AT91_PMC_IXR_LOCKB 0x00000004
147 #define AT91_PMC_IXR_MCKRDY 0x00000008 147 #define AT91_PMC_IXR_MCKRDY 0x00000008
148 #define AT91_PMC_IXR_LOCKU 0x00000040 148 #define AT91_PMC_IXR_LOCKU 0x00000040
149 #define AT91_PMC_IXR_PCKRDY0 0x00000100 149 #define AT91_PMC_IXR_PCKRDY0 0x00000100
150 #define AT91_PMC_IXR_PCKRDY1 0x00000200 150 #define AT91_PMC_IXR_PCKRDY1 0x00000200
151 #define AT91_PMC_IXR_PCKRDY2 0x00000400 151 #define AT91_PMC_IXR_PCKRDY2 0x00000400
152 #define AT91_PMC_IXR_PCKRDY3 0x00000800 152 #define AT91_PMC_IXR_PCKRDY3 0x00000800
153 #define AT91_PMC_IXR_MOSCSELS 0x00010000 153 #define AT91_PMC_IXR_MOSCSELS 0x00010000
154 154
155 #define AT91_PMC_PCR_PID_MASK (0x3f) 155 #define AT91_PMC_PCR_PID_MASK (0x3f)
156 #define AT91_PMC_PCR_CMD_WRITE (0x1 << 12) 156 #define AT91_PMC_PCR_CMD_WRITE (0x1 << 12)
157 #define AT91_PMC_PCR_EN (0x1 << 28) 157 #define AT91_PMC_PCR_EN (0x1 << 28)
158 158
159 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 159 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */
160 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 160 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
161 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 161 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
162 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 162 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
163 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 163 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
164 #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 164 #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
165 #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 165 #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
166 #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 166 #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
167 #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ 167 #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
168 #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ 168 #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
169 #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ 169 #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
170 #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ 170 #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
171 171
172 #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ 172 #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
173 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ 173 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
174 #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ 174 #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
175 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ 175 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
176 176
177 #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 177 #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
178 #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */ 178 #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
179 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 179 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
180 180
181 #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ 181 #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
182 #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ 182 #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
183 183
184 #define AT91_PMC_DIV (0xff << 0) /* Divider */ 184 #define AT91_PMC_DIV (0xff << 0) /* Divider */
185 #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 185 #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
186 #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 186 #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
187 #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ 187 #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
188 #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ 188 #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
189 #define AT91_PMC_USBDIV_1 (0 << 28) 189 #define AT91_PMC_USBDIV_1 (0 << 28)
190 #define AT91_PMC_USBDIV_2 (1 << 28) 190 #define AT91_PMC_USBDIV_2 (1 << 28)
191 #define AT91_PMC_USBDIV_4 (2 << 28) 191 #define AT91_PMC_USBDIV_4 (2 << 28)
192 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 192 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
193 #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ 193 #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
194 194
195 #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ 195 #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
196 #define AT91_PMC_CSS_SLOW (0 << 0) 196 #define AT91_PMC_CSS_SLOW (0 << 0)
197 #define AT91_PMC_CSS_MAIN (1 << 0) 197 #define AT91_PMC_CSS_MAIN (1 << 0)
198 #define AT91_PMC_CSS_PLLA (2 << 0) 198 #define AT91_PMC_CSS_PLLA (2 << 0)
199 #define AT91_PMC_CSS_PLLB (3 << 0) 199 #define AT91_PMC_CSS_PLLB (3 << 0)
200 #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ 200 #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
201 #define AT91_PMC_PRES_1 (0 << 2) 201 #define AT91_PMC_PRES_1 (0 << 2)
202 #define AT91_PMC_PRES_2 (1 << 2) 202 #define AT91_PMC_PRES_2 (1 << 2)
203 #define AT91_PMC_PRES_4 (2 << 2) 203 #define AT91_PMC_PRES_4 (2 << 2)
204 #define AT91_PMC_PRES_8 (3 << 2) 204 #define AT91_PMC_PRES_8 (3 << 2)
205 #define AT91_PMC_PRES_16 (4 << 2) 205 #define AT91_PMC_PRES_16 (4 << 2)
206 #define AT91_PMC_PRES_32 (5 << 2) 206 #define AT91_PMC_PRES_32 (5 << 2)
207 #define AT91_PMC_PRES_64 (6 << 2) 207 #define AT91_PMC_PRES_64 (6 << 2)
208 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ 208 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
209 #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ 209 #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
210 #define AT91RM9200_PMC_MDIV_2 (1 << 8) 210 #define AT91RM9200_PMC_MDIV_2 (1 << 8)
211 #define AT91RM9200_PMC_MDIV_3 (2 << 8) 211 #define AT91RM9200_PMC_MDIV_3 (2 << 8)
212 #define AT91RM9200_PMC_MDIV_4 (3 << 8) 212 #define AT91RM9200_PMC_MDIV_4 (3 << 8)
213 #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ 213 #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
214 #define AT91SAM9_PMC_MDIV_2 (1 << 8) 214 #define AT91SAM9_PMC_MDIV_2 (1 << 8)
215 #define AT91SAM9_PMC_MDIV_4 (2 << 8) 215 #define AT91SAM9_PMC_MDIV_4 (2 << 8)
216 #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ 216 #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
217 #define AT91SAM9_PMC_MDIV_6 (3 << 8) 217 #define AT91SAM9_PMC_MDIV_6 (3 << 8)
218 #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ 218 #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
219 #define AT91_PMC_PDIV_1 (0 << 12) 219 #define AT91_PMC_PDIV_1 (0 << 12)
220 #define AT91_PMC_PDIV_2 (1 << 12) 220 #define AT91_PMC_PDIV_2 (1 << 12)
221 221
222 #define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ 222 #define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
223 #define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ 223 #define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
224 #define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */ 224 #define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
225 #define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */ 225 #define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */
226 #define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */ 226 #define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
227 #define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */ 227 #define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
228 228
229 #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ 229 #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
230 #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 230 #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
231 #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 231 #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
232 #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 232 #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
233 #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock */ 233 #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock */
234 #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 234 #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
235 #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 235 #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
236 #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 236 #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
237 #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ 237 #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
238 238
239 #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ 239 #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
240 #endif 240 #endif
241 241
arch/arm/mach-at91/mpddrc.c
Diff comments   View file @ ff255e8
1 /* 1 /*
2 * Copyright (C) 2013 Atmel Corporation 2 * Copyright (C) 2013 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com> 3 * Bo Shen <voice.shen@atmel.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <asm/arch/atmel_mpddrc.h> 10 #include <asm/arch/atmel_mpddrc.h>
11 11
12 static inline void atmel_mpddr_op(int mode, u32 ram_address) 12 static inline void atmel_mpddr_op(int mode, u32 ram_address)
13 { 13 {
14 struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; 14 struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
15 15
16 writel(mode, &mpddr->mr); 16 writel(mode, &mpddr->mr);
17 writel(0, ram_address); 17 writel(0, ram_address);
18 } 18 }
19 19
20 static int ddr2_decodtype_is_seq(u32 cr) 20 static int ddr2_decodtype_is_seq(u32 cr)
21 { 21 {
22 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ 22 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
23 defined(CONFIG_AT91SAM9X5) 23 defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
24 if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) 24 if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
25 return 0; 25 return 0;
26 #endif 26 #endif
27 return 1; 27 return 1;
28 } 28 }
29 29
30 int ddr2_init(const unsigned int ram_address, 30 int ddr2_init(const unsigned int ram_address,
31 const struct atmel_mpddr *mpddr_value) 31 const struct atmel_mpddr *mpddr_value)
32 { 32 {
33 struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; 33 struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
34 u32 ba_off, cr; 34 u32 ba_off, cr;
35 35
36 /* Compute bank offset according to NC in configuration register */ 36 /* Compute bank offset according to NC in configuration register */
37 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; 37 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
38 if (ddr2_decodtype_is_seq(mpddr_value->cr)) 38 if (ddr2_decodtype_is_seq(mpddr_value->cr))
39 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; 39 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
40 40
41 ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; 41 ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
42 42
43 /* Program the memory device type into the memory device register */ 43 /* Program the memory device type into the memory device register */
44 writel(mpddr_value->md, &mpddr->md); 44 writel(mpddr_value->md, &mpddr->md);
45 45
46 /* Program the configuration register */ 46 /* Program the configuration register */
47 writel(mpddr_value->cr, &mpddr->cr); 47 writel(mpddr_value->cr, &mpddr->cr);
48 48
49 /* Program the timing register */ 49 /* Program the timing register */
50 writel(mpddr_value->tpr0, &mpddr->tpr0); 50 writel(mpddr_value->tpr0, &mpddr->tpr0);
51 writel(mpddr_value->tpr1, &mpddr->tpr1); 51 writel(mpddr_value->tpr1, &mpddr->tpr1);
52 writel(mpddr_value->tpr2, &mpddr->tpr2); 52 writel(mpddr_value->tpr2, &mpddr->tpr2);
53 53
54 /* Issue a NOP command */ 54 /* Issue a NOP command */
55 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); 55 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
56 56
57 /* A 200 us is provided to precede any signal toggle */ 57 /* A 200 us is provided to precede any signal toggle */
58 udelay(200); 58 udelay(200);
59 59
60 /* Issue a NOP command */ 60 /* Issue a NOP command */
61 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); 61 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
62 62
63 /* Issue an all banks precharge command */ 63 /* Issue an all banks precharge command */
64 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); 64 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
65 65
66 /* Issue an extended mode register set(EMRS2) to choose operation */ 66 /* Issue an extended mode register set(EMRS2) to choose operation */
67 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 67 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
68 ram_address + (0x2 << ba_off)); 68 ram_address + (0x2 << ba_off));
69 69
70 /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ 70 /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
71 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 71 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
72 ram_address + (0x3 << ba_off)); 72 ram_address + (0x3 << ba_off));
73 73
74 /* 74 /*
75 * Issue an extended mode register set(EMRS1) to enable DLL and 75 * Issue an extended mode register set(EMRS1) to enable DLL and
76 * program D.I.C (output driver impedance control) 76 * program D.I.C (output driver impedance control)
77 */ 77 */
78 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 78 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
79 ram_address + (0x1 << ba_off)); 79 ram_address + (0x1 << ba_off));
80 80
81 /* Enable DLL reset */ 81 /* Enable DLL reset */
82 cr = readl(&mpddr->cr); 82 cr = readl(&mpddr->cr);
83 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); 83 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
84 84
85 /* A mode register set(MRS) cycle is issued to reset DLL */ 85 /* A mode register set(MRS) cycle is issued to reset DLL */
86 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); 86 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
87 87
88 /* Issue an all banks precharge command */ 88 /* Issue an all banks precharge command */
89 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); 89 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
90 90
91 /* Two auto-refresh (CBR) cycles are provided */ 91 /* Two auto-refresh (CBR) cycles are provided */
92 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); 92 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
93 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); 93 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
94 94
95 /* Disable DLL reset */ 95 /* Disable DLL reset */
96 cr = readl(&mpddr->cr); 96 cr = readl(&mpddr->cr);
97 writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr); 97 writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
98 98
99 /* A mode register set (MRS) cycle is issued to disable DLL reset */ 99 /* A mode register set (MRS) cycle is issued to disable DLL reset */
100 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); 100 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
101 101
102 /* Set OCD calibration in default state */ 102 /* Set OCD calibration in default state */
103 cr = readl(&mpddr->cr); 103 cr = readl(&mpddr->cr);
104 writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); 104 writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
105 105
106 /* 106 /*
107 * An extended mode register set (EMRS1) cycle is issued 107 * An extended mode register set (EMRS1) cycle is issued
108 * to OCD default value 108 * to OCD default value
109 */ 109 */
110 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 110 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
111 ram_address + (0x1 << ba_off)); 111 ram_address + (0x1 << ba_off));
112 112
113 /* OCD calibration mode exit */ 113 /* OCD calibration mode exit */
114 cr = readl(&mpddr->cr); 114 cr = readl(&mpddr->cr);
115 writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); 115 writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
116 116
117 /* 117 /*
118 * An extended mode register set (EMRS1) cycle is issued 118 * An extended mode register set (EMRS1) cycle is issued
119 * to enable OCD exit 119 * to enable OCD exit
120 */ 120 */
121 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 121 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
122 ram_address + (0x1 << ba_off)); 122 ram_address + (0x1 << ba_off));
123 123
124 /* A nornal mode command is provided */ 124 /* A nornal mode command is provided */
125 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); 125 atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
126 126
127 /* Perform a write access to any DDR2-SDRAM address */ 127 /* Perform a write access to any DDR2-SDRAM address */
128 writel(0, ram_address); 128 writel(0, ram_address);
129 129
130 /* Write the refresh rate */ 130 /* Write the refresh rate */
131 writel(mpddr_value->rtr, &mpddr->rtr); 131 writel(mpddr_value->rtr, &mpddr->rtr);
132 132
133 return 0; 133 return 0;
134 } 134 }
135 135
arch/arm/mach-at91/spl_at91.c
Diff comments   View file @ ff255e8
1 /* 1 /*
2 * (C) Copyright 2014 DENX Software Engineering 2 * (C) Copyright 2014 DENX Software Engineering
3 * Heiko Schocher <hs@denx.de> 3 * Heiko Schocher <hs@denx.de>
4 * 4 *
5 * Based on: 5 * Based on:
6 * Copyright (C) 2013 Atmel Corporation 6 * Copyright (C) 2013 Atmel Corporation
7 * Bo Shen <voice.shen@atmel.com> 7 * Bo Shen <voice.shen@atmel.com>
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0+ 9 * SPDX-License-Identifier: GPL-2.0+
10 */ 10 */
11 11
12 #include <common.h> 12 #include <common.h>
13 #include <asm/io.h> 13 #include <asm/io.h>
14 #include <asm/arch/at91_common.h> 14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91sam9_matrix.h> 15 #include <asm/arch/at91sam9_matrix.h>
16 #include <asm/arch/at91_pit.h> 16 #include <asm/arch/at91_pit.h>
17 #include <asm/arch/at91_pmc.h> 17 #include <asm/arch/at91_pmc.h>
18 #include <asm/arch/at91_rstc.h> 18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/at91_wdt.h> 19 #include <asm/arch/at91_wdt.h>
20 #include <asm/arch/clk.h> 20 #include <asm/arch/clk.h>
21 #include <spl.h> 21 #include <spl.h>
22 22
23 DECLARE_GLOBAL_DATA_PTR; 23 DECLARE_GLOBAL_DATA_PTR;
24 24
25 static void enable_ext_reset(void) 25 static void enable_ext_reset(void)
26 { 26 {
27 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; 27 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
28 28
29 writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); 29 writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
30 } 30 }
31 31
32 void lowlevel_clock_init(void) 32 void lowlevel_clock_init(void)
33 { 33 {
34 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 34 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
35 35
36 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { 36 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
37 /* Enable Main Oscillator */ 37 /* Enable Main Oscillator */
38 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); 38 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
39 39
40 /* Wait until Main Oscillator is stable */ 40 /* Wait until Main Oscillator is stable */
41 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) 41 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
42 ; 42 ;
43 } 43 }
44 44
45 /* After stabilization, switch to Main Oscillator */ 45 /* After stabilization, switch to Main Oscillator */
46 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { 46 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
47 unsigned long tmp; 47 unsigned long tmp;
48 48
49 tmp = readl(&pmc->mckr); 49 tmp = readl(&pmc->mckr);
50 tmp &= ~AT91_PMC_CSS; 50 tmp &= ~AT91_PMC_CSS;
51 tmp |= AT91_PMC_CSS_MAIN; 51 tmp |= AT91_PMC_CSS_MAIN;
52 writel(tmp, &pmc->mckr); 52 writel(tmp, &pmc->mckr);
53 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) 53 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
54 ; 54 ;
55 55
56 tmp &= ~AT91_PMC_PRES; 56 tmp &= ~AT91_PMC_PRES;
57 tmp |= AT91_PMC_PRES_1; 57 tmp |= AT91_PMC_PRES_1;
58 writel(tmp, &pmc->mckr); 58 writel(tmp, &pmc->mckr);
59 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) 59 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
60 ; 60 ;
61 } 61 }
62 62
63 return; 63 return;
64 } 64 }
65 65
66 void __weak matrix_init(void) 66 void __weak matrix_init(void)
67 { 67 {
68 } 68 }
69 69
70 void __weak at91_spl_board_init(void) 70 void __weak at91_spl_board_init(void)
71 { 71 {
72 } 72 }
73 73
74 void __weak spl_board_init(void) 74 void __weak spl_board_init(void)
75 { 75 {
76 } 76 }
77 77
78 void board_init_f(ulong dummy) 78 void board_init_f(ulong dummy)
79 { 79 {
80 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 80 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
81 81
82 lowlevel_clock_init(); 82 lowlevel_clock_init();
83 at91_disable_wdt(); 83 at91_disable_wdt();
84 84
85 /* 85 /*
86 * At this stage the main oscillator is supposed to be enabled 86 * At this stage the main oscillator is supposed to be enabled
87 * PCK = MCK = MOSC 87 * PCK = MCK = MOSC
88 */ 88 */
89 writel(0x00, &pmc->pllicpr); 89 writel(0x00, &pmc->pllicpr);
90 90
91 /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ 91 /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
92 at91_plla_init(CONFIG_SYS_AT91_PLLA); 92 at91_plla_init(CONFIG_SYS_AT91_PLLA);
93 93
94 /* PCK = PLLA = 2 * MCK */ 94 /* PCK = PLLA = 2 * MCK */
95 at91_mck_init(CONFIG_SYS_MCKR); 95 at91_mck_init(CONFIG_SYS_MCKR);
96 96
97 /* Switch MCK on PLLA output */ 97 /* Switch MCK on PLLA output */
98 at91_mck_init(CONFIG_SYS_MCKR_CSS); 98 at91_mck_init(CONFIG_SYS_MCKR_CSS);
99 99
100 #if defined(CONFIG_SYS_AT91_PLLB) 100 #if defined(CONFIG_SYS_AT91_PLLB)
101 /* Configure PLLB */ 101 /* Configure PLLB */
102 at91_pllb_init(CONFIG_SYS_AT91_PLLB); 102 at91_pllb_init(CONFIG_SYS_AT91_PLLB);
103 #endif 103 #endif
104 104
105 /* Enable External Reset */ 105 /* Enable External Reset */
106 enable_ext_reset(); 106 enable_ext_reset();
107 107
108 /* Initialize matrix */ 108 /* Initialize matrix */
109 matrix_init(); 109 matrix_init();
110 110
111 gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; 111 gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
112 /* 112 /*
113 * init timer long enough for using in spl. 113 * init timer long enough for using in spl.
114 */ 114 */
115 timer_init(); 115 timer_init();
116 116
117 /* enable clocks for all PIOs */ 117 /* enable clocks for all PIOs */
118 #ifdef CONFIG_AT91SAM9X5 118 #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
119 at91_periph_clk_enable(ATMEL_ID_PIOAB); 119 at91_periph_clk_enable(ATMEL_ID_PIOAB);
120 at91_periph_clk_enable(ATMEL_ID_PIOCD); 120 at91_periph_clk_enable(ATMEL_ID_PIOCD);
121 #else 121 #else
122 at91_periph_clk_enable(ATMEL_ID_PIOA); 122 at91_periph_clk_enable(ATMEL_ID_PIOA);
123 at91_periph_clk_enable(ATMEL_ID_PIOB); 123 at91_periph_clk_enable(ATMEL_ID_PIOB);
124 at91_periph_clk_enable(ATMEL_ID_PIOC); 124 at91_periph_clk_enable(ATMEL_ID_PIOC);
125 #endif 125 #endif
126 /* init console */ 126 /* init console */
127 at91_seriald_hw_init(); 127 at91_seriald_hw_init();
128 preloader_console_init(); 128 preloader_console_init();
129 129
130 mem_init(); 130 mem_init();
131 131
132 at91_spl_board_init(); 132 at91_spl_board_init();
133 } 133 }
134 134
board/atmel/at91sam9n12ek/at91sam9n12ek.c
Diff comments   View file @ ff255e8
1 /* 1 /*
2 * (C) Copyright 2013 Atmel Corporation 2 * (C) Copyright 2013 Atmel Corporation
3 * Josh Wu <josh.wu@atmel.com> 3 * Josh Wu <josh.wu@atmel.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 #include <asm/arch/at91sam9x5_matrix.h> 10 #include <asm/arch/at91sam9x5_matrix.h>
11 #include <asm/arch/at91sam9_smc.h> 11 #include <asm/arch/at91sam9_smc.h>
12 #include <asm/arch/at91_common.h> 12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_pmc.h> 13 #include <asm/arch/at91_pmc.h>
14 #include <asm/arch/at91_rstc.h> 14 #include <asm/arch/at91_rstc.h>
15 #include <asm/arch/at91_pio.h> 15 #include <asm/arch/at91_pio.h>
16 #include <asm/arch/clk.h> 16 #include <asm/arch/clk.h>
17 #include <lcd.h> 17 #include <lcd.h>
18 #include <atmel_hlcdc.h> 18 #include <atmel_hlcdc.h>
19 #include <atmel_mci.h> 19 #include <atmel_mci.h>
20 #include <netdev.h> 20 #include <netdev.h>
21 21
22 #ifdef CONFIG_LCD_INFO 22 #ifdef CONFIG_LCD_INFO
23 #include <nand.h> 23 #include <nand.h>
24 #include <version.h> 24 #include <version.h>
25 #endif 25 #endif
26 26
27 DECLARE_GLOBAL_DATA_PTR; 27 DECLARE_GLOBAL_DATA_PTR;
28 28
29 /* ------------------------------------------------------------------------- */ 29 /* ------------------------------------------------------------------------- */
30 /* 30 /*
31 * Miscelaneous platform dependent initialisations 31 * Miscelaneous platform dependent initialisations
32 */ 32 */
33 #ifdef CONFIG_NAND_ATMEL 33 #ifdef CONFIG_NAND_ATMEL
34 static void at91sam9n12ek_nand_hw_init(void) 34 static void at91sam9n12ek_nand_hw_init(void)
35 { 35 {
36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
38 unsigned long csa; 38 unsigned long csa;
39 39
40 /* Assign CS3 to NAND/SmartMedia Interface */ 40 /* Assign CS3 to NAND/SmartMedia Interface */
41 csa = readl(&matrix->ebicsa); 41 csa = readl(&matrix->ebicsa);
42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
43 /* Configure databus */ 43 /* Configure databus */
44 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */ 44 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
45 /* Configure IO drive */ 45 /* Configure IO drive */
46 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 46 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
47 47
48 writel(csa, &matrix->ebicsa); 48 writel(csa, &matrix->ebicsa);
49 49
50 /* Configure SMC CS3 for NAND/SmartMedia */ 50 /* Configure SMC CS3 for NAND/SmartMedia */
51 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 51 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
52 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 52 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
53 &smc->cs[3].setup); 53 &smc->cs[3].setup);
54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
55 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 55 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
56 &smc->cs[3].pulse); 56 &smc->cs[3].pulse);
57 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7), 57 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
58 &smc->cs[3].cycle); 58 &smc->cs[3].cycle);
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE | 60 AT91_SMC_MODE_EXNW_DISABLE |
61 #ifdef CONFIG_SYS_NAND_DBW_16 61 #ifdef CONFIG_SYS_NAND_DBW_16
62 AT91_SMC_MODE_DBW_16 | 62 AT91_SMC_MODE_DBW_16 |
63 #else /* CONFIG_SYS_NAND_DBW_8 */ 63 #else /* CONFIG_SYS_NAND_DBW_8 */
64 AT91_SMC_MODE_DBW_8 | 64 AT91_SMC_MODE_DBW_8 |
65 #endif 65 #endif
66 AT91_SMC_MODE_TDF_CYCLE(1), 66 AT91_SMC_MODE_TDF_CYCLE(1),
67 &smc->cs[3].mode); 67 &smc->cs[3].mode);
68 68
69 /* Configure RDY/BSY pin */ 69 /* Configure RDY/BSY pin */
70 at91_set_pio_input(AT91_PIO_PORTD, 5, 1); 70 at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
71 71
72 /* Configure ENABLE pin for NandFlash */ 72 /* Configure ENABLE pin for NandFlash */
73 at91_set_pio_output(AT91_PIO_PORTD, 4, 1); 73 at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
74 74
75 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 75 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
76 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 76 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
77 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ 77 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
78 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ 78 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
79 } 79 }
80 #endif 80 #endif
81 81
82 #ifdef CONFIG_LCD 82 #ifdef CONFIG_LCD
83 vidinfo_t panel_info = { 83 vidinfo_t panel_info = {
84 .vl_col = 480, 84 .vl_col = 480,
85 .vl_row = 272, 85 .vl_row = 272,
86 .vl_clk = 9000000, 86 .vl_clk = 9000000,
87 .vl_bpix = LCD_BPP, 87 .vl_bpix = LCD_BPP,
88 .vl_sync = 0, 88 .vl_sync = 0,
89 .vl_tft = 1, 89 .vl_tft = 1,
90 .vl_hsync_len = 5, 90 .vl_hsync_len = 5,
91 .vl_left_margin = 8, 91 .vl_left_margin = 8,
92 .vl_right_margin = 43, 92 .vl_right_margin = 43,
93 .vl_vsync_len = 10, 93 .vl_vsync_len = 10,
94 .vl_upper_margin = 4, 94 .vl_upper_margin = 4,
95 .vl_lower_margin = 12, 95 .vl_lower_margin = 12,
96 .mmio = ATMEL_BASE_LCDC, 96 .mmio = ATMEL_BASE_LCDC,
97 }; 97 };
98 98
99 void lcd_enable(void) 99 void lcd_enable(void)
100 { 100 {
101 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */ 101 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
102 } 102 }
103 103
104 void lcd_disable(void) 104 void lcd_disable(void)
105 { 105 {
106 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */ 106 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
107 } 107 }
108 108
109 #ifdef CONFIG_LCD_INFO 109 #ifdef CONFIG_LCD_INFO
110 void lcd_show_board_info(void) 110 void lcd_show_board_info(void)
111 { 111 {
112 ulong dram_size, nand_size; 112 ulong dram_size, nand_size;
113 int i; 113 int i;
114 char temp[32]; 114 char temp[32];
115 115
116 lcd_printf("%s\n", U_BOOT_VERSION); 116 lcd_printf("%s\n", U_BOOT_VERSION);
117 lcd_printf("ATMEL Corp\n"); 117 lcd_printf("ATMEL Corp\n");
118 lcd_printf("at91@atmel.com\n"); 118 lcd_printf("at91@atmel.com\n");
119 lcd_printf("%s CPU at %s MHz\n", 119 lcd_printf("%s CPU at %s MHz\n",
120 ATMEL_CPU_NAME, 120 ATMEL_CPU_NAME,
121 strmhz(temp, get_cpu_clk_rate())); 121 strmhz(temp, get_cpu_clk_rate()));
122 122
123 dram_size = 0; 123 dram_size = 0;
124 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 124 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
125 dram_size += gd->bd->bi_dram[i].size; 125 dram_size += gd->bd->bi_dram[i].size;
126 nand_size = 0; 126 nand_size = 0;
127 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 127 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
128 nand_size += nand_info[i].size; 128 nand_size += nand_info[i].size;
129 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 129 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
130 dram_size >> 20, 130 dram_size >> 20,
131 nand_size >> 20); 131 nand_size >> 20);
132 } 132 }
133 #endif /* CONFIG_LCD_INFO */ 133 #endif /* CONFIG_LCD_INFO */
134 #endif /* CONFIG_LCD */ 134 #endif /* CONFIG_LCD */
135 135
136 /* SPI chip select control */ 136 /* SPI chip select control */
137 #ifdef CONFIG_ATMEL_SPI 137 #ifdef CONFIG_ATMEL_SPI
138 #include <spi.h> 138 #include <spi.h>
139 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 139 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
140 { 140 {
141 return bus == 0 && cs < 2; 141 return bus == 0 && cs < 2;
142 } 142 }
143 143
144 void spi_cs_activate(struct spi_slave *slave) 144 void spi_cs_activate(struct spi_slave *slave)
145 { 145 {
146 switch (slave->cs) { 146 switch (slave->cs) {
147 case 0: 147 case 0:
148 at91_set_pio_output(AT91_PIO_PORTA, 14, 0); 148 at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
149 break; 149 break;
150 case 1: 150 case 1:
151 at91_set_pio_output(AT91_PIO_PORTA, 7, 0); 151 at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
152 break; 152 break;
153 } 153 }
154 } 154 }
155 155
156 void spi_cs_deactivate(struct spi_slave *slave) 156 void spi_cs_deactivate(struct spi_slave *slave)
157 { 157 {
158 switch (slave->cs) { 158 switch (slave->cs) {
159 case 0: 159 case 0:
160 at91_set_pio_output(AT91_PIO_PORTA, 14, 1); 160 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
161 break; 161 break;
162 case 1: 162 case 1:
163 at91_set_pio_output(AT91_PIO_PORTA, 7, 1); 163 at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
164 break; 164 break;
165 } 165 }
166 } 166 }
167 #endif /* CONFIG_ATMEL_SPI */ 167 #endif /* CONFIG_ATMEL_SPI */
168 168
169 #ifdef CONFIG_GENERIC_ATMEL_MCI 169 #ifdef CONFIG_GENERIC_ATMEL_MCI
170 int board_mmc_init(bd_t *bd) 170 int board_mmc_init(bd_t *bd)
171 { 171 {
172 at91_mci_hw_init(); 172 at91_mci_hw_init();
173 173
174 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); 174 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
175 } 175 }
176 #endif 176 #endif
177 177
178 #ifdef CONFIG_KS8851_MLL 178 #ifdef CONFIG_KS8851_MLL
179 void at91sam9n12ek_ks8851_hw_init(void) 179 void at91sam9n12ek_ks8851_hw_init(void)
180 { 180 {
181 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 181 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
182 182
183 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 183 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
184 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 184 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
185 &smc->cs[2].setup); 185 &smc->cs[2].setup);
186 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 186 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
187 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), 187 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
188 &smc->cs[2].pulse); 188 &smc->cs[2].pulse);
189 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), 189 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
190 &smc->cs[2].cycle); 190 &smc->cs[2].cycle);
191 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 191 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
192 AT91_SMC_MODE_EXNW_DISABLE | 192 AT91_SMC_MODE_EXNW_DISABLE |
193 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | 193 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
194 AT91_SMC_MODE_TDF_CYCLE(1), 194 AT91_SMC_MODE_TDF_CYCLE(1),
195 &smc->cs[2].mode); 195 &smc->cs[2].mode);
196 196
197 /* Configure NCS2 PIN */ 197 /* Configure NCS2 PIN */
198 at91_set_b_periph(AT91_PIO_PORTD, 19, 0); 198 at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
199 } 199 }
200 #endif 200 #endif
201 201
202 #ifdef CONFIG_USB_ATMEL 202 #ifdef CONFIG_USB_ATMEL
203 void at91sam9n12ek_usb_hw_init(void) 203 void at91sam9n12ek_usb_hw_init(void)
204 { 204 {
205 at91_set_pio_output(AT91_PIO_PORTB, 7, 0); 205 at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
206 } 206 }
207 #endif 207 #endif
208 208
209 int board_early_init_f(void) 209 int board_early_init_f(void)
210 { 210 {
211 /* Enable clocks for all PIOs */ 211 /* Enable clocks for all PIOs */
212 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 212 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
213 writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer); 213 writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
214 214
215 at91_seriald_hw_init(); 215 at91_seriald_hw_init();
216 return 0; 216 return 0;
217 } 217 }
218 218
219 int board_init(void) 219 int board_init(void)
220 { 220 {
221 /* adress of boot parameters */ 221 /* adress of boot parameters */
222 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 222 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
223 223
224 #ifdef CONFIG_NAND_ATMEL 224 #ifdef CONFIG_NAND_ATMEL
225 at91sam9n12ek_nand_hw_init(); 225 at91sam9n12ek_nand_hw_init();
226 #endif 226 #endif
227 227
228 #ifdef CONFIG_ATMEL_SPI 228 #ifdef CONFIG_ATMEL_SPI
229 at91_spi0_hw_init(1 << 0); 229 at91_spi0_hw_init(1 << 0);
230 #endif 230 #endif
231 231
232 #ifdef CONFIG_LCD 232 #ifdef CONFIG_LCD
233 at91_lcd_hw_init(); 233 at91_lcd_hw_init();
234 #endif 234 #endif
235 235
236 #ifdef CONFIG_KS8851_MLL 236 #ifdef CONFIG_KS8851_MLL
237 at91sam9n12ek_ks8851_hw_init(); 237 at91sam9n12ek_ks8851_hw_init();
238 #endif 238 #endif
239 239
240 #ifdef CONFIG_USB_ATMEL 240 #ifdef CONFIG_USB_ATMEL
241 at91sam9n12ek_usb_hw_init(); 241 at91sam9n12ek_usb_hw_init();
242 #endif 242 #endif
243 243
244 return 0; 244 return 0;
245 } 245 }
246 246
247 #ifdef CONFIG_KS8851_MLL 247 #ifdef CONFIG_KS8851_MLL
248 int board_eth_init(bd_t *bis) 248 int board_eth_init(bd_t *bis)
249 { 249 {
250 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); 250 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
251 } 251 }
252 #endif 252 #endif
253 253
254 int dram_init(void) 254 int dram_init(void)
255 { 255 {
256 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 256 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
257 CONFIG_SYS_SDRAM_SIZE); 257 CONFIG_SYS_SDRAM_SIZE);
258 return 0; 258 return 0;
259 } 259 }
260
261 #if defined(CONFIG_SPL_BUILD)
262 #include <spl.h>
263 #include <nand.h>
264
265 void at91_spl_board_init(void)
266 {
267 #ifdef CONFIG_SYS_USE_MMC
268 at91_mci_hw_init();
269 #elif CONFIG_SYS_USE_NANDFLASH
270 at91sam9n12ek_nand_hw_init();
271 #elif CONFIG_SYS_USE_SPIFLASH
272 at91_spi0_hw_init(1 << 4);
273 #endif
274 }
275
276 #include <asm/arch/atmel_mpddrc.h>
277 static void ddr2_conf(struct atmel_mpddr *ddr2)
278 {
279 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
280
281 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
282 ATMEL_MPDDRC_CR_NR_ROW_13 |
283 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
284 ATMEL_MPDDRC_CR_NB_8BANKS |
285 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
286
287 ddr2->rtr = 0x411;
288
289 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
290 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
291 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
292 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
293 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
294 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
295 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
296 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
297
298 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
299 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
300 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
301 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
302
303 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
304 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
305 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
306 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
307 }
308
309 void mem_init(void)
310 {
311 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
312 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
313 struct atmel_mpddr ddr2;
314 unsigned long csa;
315
316 ddr2_conf(&ddr2);
317
318 /* enable DDR2 clock */
319 writel(0x4, &pmc->scer);
320
321 /* Chip select 1 is for DDR2/SDRAM */
322 csa = readl(&matrix->ebicsa);
323 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
324 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
325 csa |= AT91_MATRIX_EBI_DBPD_OFF;
326 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
327 writel(csa, &matrix->ebicsa);
328
329 /* DDRAM2 Controller initialize */
330 ddr2_init(ATMEL_BASE_CS1, &ddr2);
331 }
332 #endif
260 333
configs/at91sam9n12ek_nandflash_defconfig
Diff comments   View file @ ff255e8
1 CONFIG_SPL=y
1 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" 2 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
2 CONFIG_ARM=y 3 CONFIG_ARM=y
3 CONFIG_ARCH_AT91=y 4 CONFIG_ARCH_AT91=y
4 CONFIG_TARGET_AT91SAM9N12EK=y 5 CONFIG_TARGET_AT91SAM9N12EK=y
5 6
configs/at91sam9n12ek_spiflash_defconfig
Diff comments   View file @ ff255e8
1 CONFIG_SPL=y
1 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" 2 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
2 CONFIG_ARM=y 3 CONFIG_ARM=y
3 CONFIG_ARCH_AT91=y 4 CONFIG_ARCH_AT91=y
4 CONFIG_TARGET_AT91SAM9N12EK=y 5 CONFIG_TARGET_AT91SAM9N12EK=y
5 6
include/configs/at91sam9n12ek.h
Diff comments   View file @ ff255e8
1 /* 1 /*
2 * (C) Copyright 2013 Atmel Corporation. 2 * (C) Copyright 2013 Atmel Corporation.
3 * Josh Wu <josh.wu@atmel.com> 3 * Josh Wu <josh.wu@atmel.com>
4 * 4 *
5 * Configuation settings for the AT91SAM9N12-EK boards. 5 * Configuation settings for the AT91SAM9N12-EK boards.
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #ifndef __AT91SAM9N12_CONFIG_H_ 10 #ifndef __AT91SAM9N12_CONFIG_H_
11 #define __AT91SAM9N12_CONFIG_H_ 11 #define __AT91SAM9N12_CONFIG_H_
12 12
13 /* 13 /*
14 * SoC must be defined first, before hardware.h is included. 14 * SoC must be defined first, before hardware.h is included.
15 * In this case SoC is defined in boards.cfg. 15 * In this case SoC is defined in boards.cfg.
16 */ 16 */
17 #include <asm/hardware.h> 17 #include <asm/hardware.h>
18 18
19 #define CONFIG_SYS_TEXT_BASE 0x26f00000 19 #define CONFIG_SYS_TEXT_BASE 0x26f00000
20 20
21 /* ARM asynchronous clock */ 21 /* ARM asynchronous clock */
22 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 22 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
23 #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ 23 #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
24 24
25 /* Misc CPU related */ 25 /* Misc CPU related */
26 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 26 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
27 #define CONFIG_SETUP_MEMORY_TAGS 27 #define CONFIG_SETUP_MEMORY_TAGS
28 #define CONFIG_INITRD_TAG 28 #define CONFIG_INITRD_TAG
29 #define CONFIG_SKIP_LOWLEVEL_INIT 29 #define CONFIG_SKIP_LOWLEVEL_INIT
30 #define CONFIG_BOARD_EARLY_INIT_F 30 #define CONFIG_BOARD_EARLY_INIT_F
31 #define CONFIG_DISPLAY_CPUINFO 31 #define CONFIG_DISPLAY_CPUINFO
32 32
33 #define CONFIG_OF_LIBFDT 33 #define CONFIG_OF_LIBFDT
34 #define CONFIG_SYS_GENERIC_BOARD 34 #define CONFIG_SYS_GENERIC_BOARD
35 35
36 /* general purpose I/O */ 36 /* general purpose I/O */
37 #define CONFIG_AT91_GPIO 37 #define CONFIG_AT91_GPIO
38 38
39 /* serial console */ 39 /* serial console */
40 #define CONFIG_ATMEL_USART 40 #define CONFIG_ATMEL_USART
41 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 41 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
42 #define CONFIG_USART_ID ATMEL_ID_SYS 42 #define CONFIG_USART_ID ATMEL_ID_SYS
43 #define CONFIG_BAUDRATE 115200 43 #define CONFIG_BAUDRATE 115200
44 44
45 /* LCD */ 45 /* LCD */
46 #define CONFIG_LCD 46 #define CONFIG_LCD
47 #define LCD_BPP LCD_COLOR16 47 #define LCD_BPP LCD_COLOR16
48 #define LCD_OUTPUT_BPP 24 48 #define LCD_OUTPUT_BPP 24
49 #define CONFIG_LCD_LOGO 49 #define CONFIG_LCD_LOGO
50 #define CONFIG_LCD_INFO 50 #define CONFIG_LCD_INFO
51 #define CONFIG_LCD_INFO_BELOW_LOGO 51 #define CONFIG_LCD_INFO_BELOW_LOGO
52 #define CONFIG_SYS_WHITE_ON_BLACK 52 #define CONFIG_SYS_WHITE_ON_BLACK
53 #define CONFIG_ATMEL_HLCD 53 #define CONFIG_ATMEL_HLCD
54 #define CONFIG_ATMEL_LCD_RGB565 54 #define CONFIG_ATMEL_LCD_RGB565
55 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 55 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
56 56
57 #define CONFIG_BOOTDELAY 3 57 #define CONFIG_BOOTDELAY 3
58 58
59 /* 59 /*
60 * BOOTP options 60 * BOOTP options
61 */ 61 */
62 #define CONFIG_BOOTP_BOOTFILESIZE 62 #define CONFIG_BOOTP_BOOTFILESIZE
63 #define CONFIG_BOOTP_BOOTPATH 63 #define CONFIG_BOOTP_BOOTPATH
64 #define CONFIG_BOOTP_GATEWAY 64 #define CONFIG_BOOTP_GATEWAY
65 #define CONFIG_BOOTP_HOSTNAME 65 #define CONFIG_BOOTP_HOSTNAME
66 66
67 /* NOR flash - no real flash on this board */ 67 /* NOR flash - no real flash on this board */
68 #define CONFIG_SYS_NO_FLASH 68 #define CONFIG_SYS_NO_FLASH
69 69
70 /* 70 /*
71 * Command line configuration. 71 * Command line configuration.
72 */ 72 */
73 #include <config_cmd_default.h> 73 #include <config_cmd_default.h>
74 #undef CONFIG_CMD_FPGA 74 #undef CONFIG_CMD_FPGA
75 75
76 #define CONFIG_CMD_BOOTZ 76 #define CONFIG_CMD_BOOTZ
77 #define CONFIG_CMD_PING 77 #define CONFIG_CMD_PING
78 #define CONFIG_CMD_DHCP 78 #define CONFIG_CMD_DHCP
79 #define CONFIG_CMD_NAND 79 #define CONFIG_CMD_NAND
80 #define CONFIG_CMD_SF 80 #define CONFIG_CMD_SF
81 #define CONFIG_CMD_MMC 81 #define CONFIG_CMD_MMC
82 #define CONFIG_CMD_FAT 82 #define CONFIG_CMD_FAT
83 #define CONFIG_CMD_USB 83 #define CONFIG_CMD_USB
84 84
85 #define CONFIG_NR_DRAM_BANKS 1 85 #define CONFIG_NR_DRAM_BANKS 1
86 #define CONFIG_SYS_SDRAM_BASE 0x20000000 86 #define CONFIG_SYS_SDRAM_BASE 0x20000000
87 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 87 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
88 88
89 /* 89 /*
90 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, 90 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
91 * leaving the correct space for initial global data structure above 91 * leaving the correct space for initial global data structure above
92 * that address while providing maximum stack area below. 92 * that address while providing maximum stack area below.
93 */ 93 */
94 # define CONFIG_SYS_INIT_SP_ADDR \ 94 # define CONFIG_SYS_INIT_SP_ADDR \
95 (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE) 95 (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
96 96
97 /* DataFlash */ 97 /* DataFlash */
98 #ifdef CONFIG_CMD_SF 98 #ifdef CONFIG_CMD_SF
99 #define CONFIG_ATMEL_SPI 99 #define CONFIG_ATMEL_SPI
100 #define CONFIG_SPI_FLASH 100 #define CONFIG_SPI_FLASH
101 #define CONFIG_SPI_FLASH_ATMEL 101 #define CONFIG_SPI_FLASH_ATMEL
102 #define CONFIG_SF_DEFAULT_SPEED 30000000 102 #define CONFIG_SF_DEFAULT_SPEED 30000000
103 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 103 #define CONFIG_ENV_SPI_MODE SPI_MODE_3
104 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 104 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
105 #endif 105 #endif
106 106
107 /* NAND flash */ 107 /* NAND flash */
108 #ifdef CONFIG_CMD_NAND 108 #ifdef CONFIG_CMD_NAND
109 #define CONFIG_NAND_ATMEL 109 #define CONFIG_NAND_ATMEL
110 #define CONFIG_SYS_MAX_NAND_DEVICE 1 110 #define CONFIG_SYS_MAX_NAND_DEVICE 1
111 #define CONFIG_SYS_NAND_BASE 0x40000000 111 #define CONFIG_SYS_NAND_BASE 0x40000000
112 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 112 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
113 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 113 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
114 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4) 114 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
115 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) 115 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
116 116
117 /* PMECC & PMERRLOC */ 117 /* PMECC & PMERRLOC */
118 #define CONFIG_ATMEL_NAND_HWECC 118 #define CONFIG_ATMEL_NAND_HWECC
119 #define CONFIG_ATMEL_NAND_HW_PMECC 119 #define CONFIG_ATMEL_NAND_HW_PMECC
120 #define CONFIG_PMECC_CAP 2 120 #define CONFIG_PMECC_CAP 2
121 #define CONFIG_PMECC_SECTOR_SIZE 512 121 #define CONFIG_PMECC_SECTOR_SIZE 512
122 #define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 122 #define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
123 123
124 #define CONFIG_CMD_NAND_TRIMFFS 124 #define CONFIG_CMD_NAND_TRIMFFS
125 125
126 #endif 126 #endif
127 127
128 #define CONFIG_MTD_PARTITIONS 128 #define CONFIG_MTD_PARTITIONS
129 #define CONFIG_MTD_DEVICE 129 #define CONFIG_MTD_DEVICE
130 #define CONFIG_CMD_MTDPARTS 130 #define CONFIG_CMD_MTDPARTS
131 #define MTDIDS_DEFAULT "nand0=atmel_nand" 131 #define MTDIDS_DEFAULT "nand0=atmel_nand"
132 #define MTDPARTS_DEFAULT \ 132 #define MTDPARTS_DEFAULT \
133 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 133 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
134 "256k(env),256k(env_redundant),256k(spare)," \ 134 "256k(env),256k(env_redundant),256k(spare)," \
135 "512k(dtb),6M(kernel)ro,-(rootfs)" 135 "512k(dtb),6M(kernel)ro,-(rootfs)"
136 136
137 #define CONFIG_EXTRA_ENV_SETTINGS \ 137 #define CONFIG_EXTRA_ENV_SETTINGS \
138 "console=console=ttyS0,115200\0" \ 138 "console=console=ttyS0,115200\0" \
139 "mtdparts="MTDPARTS_DEFAULT"\0" \ 139 "mtdparts="MTDPARTS_DEFAULT"\0" \
140 "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ 140 "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
141 "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" 141 "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
142 142
143 /* MMC */ 143 /* MMC */
144 #ifdef CONFIG_CMD_MMC 144 #ifdef CONFIG_CMD_MMC
145 #define CONFIG_MMC 145 #define CONFIG_MMC
146 #define CONFIG_GENERIC_MMC 146 #define CONFIG_GENERIC_MMC
147 #define CONFIG_GENERIC_ATMEL_MCI 147 #define CONFIG_GENERIC_ATMEL_MCI
148 #endif 148 #endif
149 149
150 /* FAT */ 150 /* FAT */
151 #ifdef CONFIG_CMD_FAT 151 #ifdef CONFIG_CMD_FAT
152 #define CONFIG_DOS_PARTITION 152 #define CONFIG_DOS_PARTITION
153 #endif 153 #endif
154 154
155 /* Ethernet */ 155 /* Ethernet */
156 #define CONFIG_KS8851_MLL 156 #define CONFIG_KS8851_MLL
157 #define CONFIG_KS8851_MLL_BASEADDR 0x30000000 /* use NCS2 */ 157 #define CONFIG_KS8851_MLL_BASEADDR 0x30000000 /* use NCS2 */
158 158
159 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 159 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
160 160
161 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 161 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
162 #define CONFIG_SYS_MEMTEST_END 0x26e00000 162 #define CONFIG_SYS_MEMTEST_END 0x26e00000
163 163
164 /* USB host */ 164 /* USB host */
165 #ifdef CONFIG_CMD_USB 165 #ifdef CONFIG_CMD_USB
166 #define CONFIG_USB_ATMEL 166 #define CONFIG_USB_ATMEL
167 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 167 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
168 #define CONFIG_USB_OHCI_NEW 168 #define CONFIG_USB_OHCI_NEW
169 #define CONFIG_SYS_USB_OHCI_CPU_INIT 169 #define CONFIG_SYS_USB_OHCI_CPU_INIT
170 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 170 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
171 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12" 171 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12"
172 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 172 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
173 #define CONFIG_USB_STORAGE 173 #define CONFIG_USB_STORAGE
174 #endif 174 #endif
175 175
176 #ifdef CONFIG_SYS_USE_SPIFLASH 176 #ifdef CONFIG_SYS_USE_SPIFLASH
177 177
178 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 178 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
179 #define CONFIG_ENV_IS_IN_SPI_FLASH 179 #define CONFIG_ENV_IS_IN_SPI_FLASH
180 #define CONFIG_ENV_OFFSET 0x5000 180 #define CONFIG_ENV_OFFSET 0x5000
181 #define CONFIG_ENV_SIZE 0x3000 181 #define CONFIG_ENV_SIZE 0x3000
182 #define CONFIG_ENV_SECT_SIZE 0x1000 182 #define CONFIG_ENV_SECT_SIZE 0x1000
183 #define CONFIG_BOOTCOMMAND \ 183 #define CONFIG_BOOTCOMMAND \
184 "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \ 184 "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \
185 "sf probe 0; sf read 0x22000000 0x100000 0x300000; " \ 185 "sf probe 0; sf read 0x22000000 0x100000 0x300000; " \
186 "bootm 0x22000000" 186 "bootm 0x22000000"
187 187
188 #elif defined(CONFIG_SYS_USE_NANDFLASH) 188 #elif defined(CONFIG_SYS_USE_NANDFLASH)
189 189
190 /* bootstrap + u-boot + env + linux in nandflash */ 190 /* bootstrap + u-boot + env + linux in nandflash */
191 #define CONFIG_ENV_IS_IN_NAND 191 #define CONFIG_ENV_IS_IN_NAND
192 #define CONFIG_ENV_OFFSET 0xc0000 192 #define CONFIG_ENV_OFFSET 0xc0000
193 #define CONFIG_ENV_OFFSET_REDUND 0x100000 193 #define CONFIG_ENV_OFFSET_REDUND 0x100000
194 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 194 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
195 #define CONFIG_BOOTCOMMAND \ 195 #define CONFIG_BOOTCOMMAND \
196 "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \ 196 "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \
197 "nand read 0x21000000 0x180000 0x080000;" \ 197 "nand read 0x21000000 0x180000 0x080000;" \
198 "nand read 0x22000000 0x200000 0x400000;" \ 198 "nand read 0x22000000 0x200000 0x400000;" \
199 "bootm 0x22000000 - 0x21000000" 199 "bootm 0x22000000 - 0x21000000"
200 200
201 #else /* CONFIG_SYS_USE_MMC */ 201 #else /* CONFIG_SYS_USE_MMC */
202 202
203 /* bootstrap + u-boot + env + linux in mmc */ 203 /* bootstrap + u-boot + env + linux in mmc */
204 204
205 #ifdef CONFIG_ENV_IS_IN_MMC 205 #ifdef CONFIG_ENV_IS_IN_MMC
206 /* Use raw reserved sectors to save environment */ 206 /* Use raw reserved sectors to save environment */
207 #define CONFIG_ENV_OFFSET 0x2000 207 #define CONFIG_ENV_OFFSET 0x2000
208 #define CONFIG_ENV_SIZE 0x1000 208 #define CONFIG_ENV_SIZE 0x1000
209 #define CONFIG_SYS_MMC_ENV_DEV 0 209 #define CONFIG_SYS_MMC_ENV_DEV 0
210 #else 210 #else
211 /* Use file in FAT file to save environment */ 211 /* Use file in FAT file to save environment */
212 #define CONFIG_ENV_IS_IN_FAT 212 #define CONFIG_ENV_IS_IN_FAT
213 #define CONFIG_FAT_WRITE 213 #define CONFIG_FAT_WRITE
214 #define FAT_ENV_INTERFACE "mmc" 214 #define FAT_ENV_INTERFACE "mmc"
215 #define FAT_ENV_FILE "uboot.env" 215 #define FAT_ENV_FILE "uboot.env"
216 #define FAT_ENV_DEVICE_AND_PART "0" 216 #define FAT_ENV_DEVICE_AND_PART "0"
217 #define CONFIG_ENV_SIZE 0x4000 217 #define CONFIG_ENV_SIZE 0x4000
218 #endif 218 #endif
219 219
220 #define CONFIG_BOOTCOMMAND \ 220 #define CONFIG_BOOTCOMMAND \
221 "setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};" \ 221 "setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};" \
222 "fatload mmc 0:1 0x21000000 dtb;" \ 222 "fatload mmc 0:1 0x21000000 dtb;" \
223 "fatload mmc 0:1 0x22000000 uImage;" \ 223 "fatload mmc 0:1 0x22000000 uImage;" \
224 "bootm 0x22000000 - 0x21000000" 224 "bootm 0x22000000 - 0x21000000"
225 225
226 #endif 226 #endif
227 227
228 #define CONFIG_SYS_PROMPT "U-Boot> " 228 #define CONFIG_SYS_PROMPT "U-Boot> "
229 #define CONFIG_SYS_CBSIZE 256 229 #define CONFIG_SYS_CBSIZE 256
230 #define CONFIG_SYS_MAXARGS 16 230 #define CONFIG_SYS_MAXARGS 16
231 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \ 231 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
232 + 16) 232 + 16)
233 #define CONFIG_SYS_LONGHELP 233 #define CONFIG_SYS_LONGHELP
234 #define CONFIG_CMDLINE_EDITING 234 #define CONFIG_CMDLINE_EDITING
235 #define CONFIG_AUTO_COMPLETE 235 #define CONFIG_AUTO_COMPLETE
236 #define CONFIG_SYS_HUSH_PARSER 236 #define CONFIG_SYS_HUSH_PARSER
237 237
238 /* 238 /*
239 * Size of malloc() pool 239 * Size of malloc() pool
240 */ 240 */
241 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 241 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
242 #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ 242
243 /* SPL */
244 #define CONFIG_SPL_FRAMEWORK
245 #define CONFIG_SPL_TEXT_BASE 0x300000
246 #define CONFIG_SPL_MAX_SIZE 0x6000
247 #define CONFIG_SPL_STACK 0x308000
248
249 #define CONFIG_SPL_BSS_START_ADDR 0x20000000
250 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
251 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
252 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
253
254 #define CONFIG_SPL_LIBCOMMON_SUPPORT
255 #define CONFIG_SPL_LIBGENERIC_SUPPORT
256 #define CONFIG_SPL_GPIO_SUPPORT
257 #define CONFIG_SPL_SERIAL_SUPPORT
258
259 #define CONFIG_SPL_BOARD_INIT
260 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
261
262 #define CONFIG_SYS_MASTER_CLOCK 132096000
263 #define CONFIG_SYS_AT91_PLLA 0x20953f03
264 #define CONFIG_SYS_MCKR 0x1301
265 #define CONFIG_SYS_MCKR_CSS 0x1302
266
267 #define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
268
269 #ifdef CONFIG_SYS_USE_MMC
270 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
271 #define CONFIG_SPL_MMC_SUPPORT
272 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
273 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
274 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
275 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
276 #define CONFIG_SPL_FAT_SUPPORT
277 #define CONFIG_SPL_LIBDISK_SUPPORT
278
279 #elif CONFIG_SYS_USE_NANDFLASH
280 #define CONFIG_SPL_NAND_SUPPORT
281 #define CONFIG_SPL_NAND_DRIVERS
282 #define CONFIG_SPL_NAND_BASE
283 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
284 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
285 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
286 #define CONFIG_SYS_NAND_PAGE_COUNT 64
287 #define CONFIG_SYS_NAND_OOBSIZE 64
288 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
289 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
290 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
291
292 #elif CONFIG_SYS_USE_SPIFLASH
293 #define CONFIG_SPL_SPI_SUPPORT
294 #define CONFIG_SPL_SPI_FLASH_SUPPORT
295 #define CONFIG_SPL_SPI_LOAD
296 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
297
298 #endif
243 299
244 #endif 300 #endif
245 301