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Commit ff255e836a3a6cd52bd51a192af96ac5f224dc22

Authored by Bo Shen
Committed by Andreas Bießmann
1 parent d85e8914b3
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: atmel: at91sam9n12ek: enable spl support 

Enable SPL support for at91sam9n12ek boards, now it supports
boot up from NAND flash, serial flash.

Signed-off-by: Bo Shen <voice.shen@atmel.com>

Showing 9 changed files with 138 additions and 5 deletions Side-by-side Diff

arch/arm/mach-at91/Kconfig
Diff comments   View file @ ff255e8
... ... @@ -75,6 +75,7 @@
75 75 config TARGET_AT91SAM9N12EK
76 76 bool "Atmel AT91SAM9N12-EK board"
77 77 select CPU_ARM926EJS
  78 + select SUPPORT_SPL
78 79  
79 80 config TARGET_AT91SAM9RLEK
80 81 bool "Atmel at91sam9rl reference board"
arch/arm/mach-at91/Makefile
Diff comments   View file @ ff255e8
... ... @@ -2,6 +2,7 @@
2 2 ifneq ($(CONFIG_SPL_BUILD),)
3 3 obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
4 4 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
  5 +obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
5 6 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
6 7 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
7 8 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
arch/arm/mach-at91/include/mach/at91_pmc.h
Diff comments   View file @ ff255e8
... ... @@ -98,7 +98,7 @@
98 98 #define AT91_PMC_MCKR_CSS_MASK 0x00000003
99 99  
100 100 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
101   - defined(CONFIG_AT91SAM9X5)
  101 + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
102 102 #define AT91_PMC_MCKR_PRES_1 0x00000000
103 103 #define AT91_PMC_MCKR_PRES_2 0x00000010
104 104 #define AT91_PMC_MCKR_PRES_4 0x00000020
... ... @@ -128,7 +128,7 @@
128 128 #define AT91_PMC_MCKR_MDIV_1 0x00000000
129 129 #define AT91_PMC_MCKR_MDIV_2 0x00000100
130 130 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
131   - defined(CONFIG_AT91SAM9X5)
  131 + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
132 132 #define AT91_PMC_MCKR_MDIV_3 0x00000300
133 133 #endif
134 134 #define AT91_PMC_MCKR_MDIV_4 0x00000200
arch/arm/mach-at91/mpddrc.c
Diff comments   View file @ ff255e8
... ... @@ -20,7 +20,7 @@
20 20 static int ddr2_decodtype_is_seq(u32 cr)
21 21 {
22 22 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
23   - defined(CONFIG_AT91SAM9X5)
  23 + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
24 24 if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
25 25 return 0;
26 26 #endif
arch/arm/mach-at91/spl_at91.c
Diff comments   View file @ ff255e8
... ... @@ -115,7 +115,7 @@
115 115 timer_init();
116 116  
117 117 /* enable clocks for all PIOs */
118   -#ifdef CONFIG_AT91SAM9X5
  118 +#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
119 119 at91_periph_clk_enable(ATMEL_ID_PIOAB);
120 120 at91_periph_clk_enable(ATMEL_ID_PIOCD);
121 121 #else
board/atmel/at91sam9n12ek/at91sam9n12ek.c
Diff comments   View file @ ff255e8
... ... @@ -257,4 +257,77 @@
257 257 CONFIG_SYS_SDRAM_SIZE);
258 258 return 0;
259 259 }
  260 +
  261 +#if defined(CONFIG_SPL_BUILD)
  262 +#include <spl.h>
  263 +#include <nand.h>
  264 +
  265 +void at91_spl_board_init(void)
  266 +{
  267 +#ifdef CONFIG_SYS_USE_MMC
  268 + at91_mci_hw_init();
  269 +#elif CONFIG_SYS_USE_NANDFLASH
  270 + at91sam9n12ek_nand_hw_init();
  271 +#elif CONFIG_SYS_USE_SPIFLASH
  272 + at91_spi0_hw_init(1 << 4);
  273 +#endif
  274 +}
  275 +
  276 +#include <asm/arch/atmel_mpddrc.h>
  277 +static void ddr2_conf(struct atmel_mpddr *ddr2)
  278 +{
  279 + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  280 +
  281 + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  282 + ATMEL_MPDDRC_CR_NR_ROW_13 |
  283 + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  284 + ATMEL_MPDDRC_CR_NB_8BANKS |
  285 + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
  286 +
  287 + ddr2->rtr = 0x411;
  288 +
  289 + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  290 + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  291 + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  292 + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  293 + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  294 + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  295 + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  296 + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  297 +
  298 + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  299 + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  300 + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  301 + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  302 +
  303 + ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  304 + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  305 + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  306 + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  307 +}
  308 +
  309 +void mem_init(void)
  310 +{
  311 + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  312 + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  313 + struct atmel_mpddr ddr2;
  314 + unsigned long csa;
  315 +
  316 + ddr2_conf(&ddr2);
  317 +
  318 + /* enable DDR2 clock */
  319 + writel(0x4, &pmc->scer);
  320 +
  321 + /* Chip select 1 is for DDR2/SDRAM */
  322 + csa = readl(&matrix->ebicsa);
  323 + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  324 + csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
  325 + csa |= AT91_MATRIX_EBI_DBPD_OFF;
  326 + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  327 + writel(csa, &matrix->ebicsa);
  328 +
  329 + /* DDRAM2 Controller initialize */
  330 + ddr2_init(ATMEL_BASE_CS1, &ddr2);
  331 +}
  332 +#endif
configs/at91sam9n12ek_nandflash_defconfig
Diff comments   View file @ ff255e8
  1 +CONFIG_SPL=y
1 2 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
2 3 CONFIG_ARM=y
3 4 CONFIG_ARCH_AT91=y
configs/at91sam9n12ek_spiflash_defconfig
Diff comments   View file @ ff255e8
  1 +CONFIG_SPL=y
1 2 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
2 3 CONFIG_ARM=y
3 4 CONFIG_ARCH_AT91=y
include/configs/at91sam9n12ek.h
Diff comments   View file @ ff255e8
... ... @@ -239,7 +239,63 @@
239 239 * Size of malloc() pool
240 240 */
241 241 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
242   -#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
  242 +
  243 +/* SPL */
  244 +#define CONFIG_SPL_FRAMEWORK
  245 +#define CONFIG_SPL_TEXT_BASE 0x300000
  246 +#define CONFIG_SPL_MAX_SIZE 0x6000
  247 +#define CONFIG_SPL_STACK 0x308000
  248 +
  249 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000
  250 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  251 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
  252 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  253 +
  254 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  255 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  256 +#define CONFIG_SPL_GPIO_SUPPORT
  257 +#define CONFIG_SPL_SERIAL_SUPPORT
  258 +
  259 +#define CONFIG_SPL_BOARD_INIT
  260 +#define CONFIG_SYS_MONITOR_LEN (512 << 10)
  261 +
  262 +#define CONFIG_SYS_MASTER_CLOCK 132096000
  263 +#define CONFIG_SYS_AT91_PLLA 0x20953f03
  264 +#define CONFIG_SYS_MCKR 0x1301
  265 +#define CONFIG_SYS_MCKR_CSS 0x1302
  266 +
  267 +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
  268 +
  269 +#ifdef CONFIG_SYS_USE_MMC
  270 +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
  271 +#define CONFIG_SPL_MMC_SUPPORT
  272 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
  273 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
  274 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  275 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  276 +#define CONFIG_SPL_FAT_SUPPORT
  277 +#define CONFIG_SPL_LIBDISK_SUPPORT
  278 +
  279 +#elif CONFIG_SYS_USE_NANDFLASH
  280 +#define CONFIG_SPL_NAND_SUPPORT
  281 +#define CONFIG_SPL_NAND_DRIVERS
  282 +#define CONFIG_SPL_NAND_BASE
  283 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  284 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  285 +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
  286 +#define CONFIG_SYS_NAND_PAGE_COUNT 64
  287 +#define CONFIG_SYS_NAND_OOBSIZE 64
  288 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
  289 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
  290 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
  291 +
  292 +#elif CONFIG_SYS_USE_SPIFLASH
  293 +#define CONFIG_SPL_SPI_SUPPORT
  294 +#define CONFIG_SPL_SPI_FLASH_SUPPORT
  295 +#define CONFIG_SPL_SPI_LOAD
  296 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
  297 +
  298 +#endif
243 299  
244 300 #endif