Eric Lee / smarc-uboot

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Commit ff36fd8591776405eeb3a086ba1136bf1ece2ffb

Authored by wdenk
1 parent 6310eb9da7
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Patch by Leif Lindholm, 23 Sep 2004: 

add support for the AMD db1550 board

* Patch by Travis Sawyer, 15 Sep 2004:
  Add CONFIG_SERIAL_MULTI support for ppc4xx,
  update README.serial_multi

Showing 14 changed files with 607 additions and 53 deletions Side-by-side Diff

... ... @@ -2,6 +2,13 @@
2 2 Changes for U-Boot 1.1.3:
3 3 ======================================================================
4 4  
  5 +* Patch by Leif Lindholm, 23 Sep 2004:
  6 + add support for the AMD db1550 board
  7 +
  8 +* Patch by Travis Sawyer, 15 Sep 2004:
  9 + Add CONFIG_SERIAL_MULTI support for ppc4xx,
  10 + update README.serial_multi
  11 +
5 12 * Patches by David Snowdon, 07 Sep 2004:
6 13 - add u-boot.hex target in the top level Makefile
7 14 - add support for the UNSW/NICTA PLEB 2 board (pleb2)
... ... @@ -253,6 +253,10 @@
253 253 D: Support for LEOX boards, DS164x RTC
254 254 W: http://www.leox.org
255 255  
  256 +N: Leif Lindholm
  257 +E: leif.lindholm@i3micro.com
  258 +D: Support for AMD dbau1550 board.
  259 +
256 260 N: Stephan Linz
257 261 E: linz@li-pro.net
258 262 D: Support for Nios Stratix Development Kit (DK-1S10)
... ... @@ -180,9 +180,9 @@
180 180  
181 181 LIST_mips5kc="purple"
182 182  
183   -LIST_au1x00="dbau1000 dbau1100 dbau1500"
  183 +LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
184 184  
185   -LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"
  185 +LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
186 186  
187 187 #########################################################################
188 188 ## i386 Systems
... ... @@ -1467,6 +1467,16 @@
1467 1467 @echo "#define CONFIG_DBAU1500 1" >>include/config.h
1468 1468 @./mkconfig -a dbau1x00 mips mips dbau1x00
1469 1469  
  1470 +dbau1550_config : unconfig
  1471 + @ >include/config.h
  1472 + @echo "#define CONFIG_DBAU1550 1" >>include/config.h
  1473 + @./mkconfig -a dbau1x00 mips mips dbau1x00
  1474 +
  1475 +dbau1550_el_config : unconfig
  1476 + @ >include/config.h
  1477 + @echo "#define CONFIG_DBAU1550 1" >>include/config.h
  1478 + @./mkconfig -a dbau1x00 mips mips dbau1x00 "" little
  1479 +
1470 1480 #########################################################################
1471 1481 ## MIPS64 5Kc
1472 1482 #########################################################################
board/dbau1x00/dbau1x00.c
Diff comments   View file @ ff36fd8
... ... @@ -30,7 +30,7 @@
30 30 {
31 31 /* Sdram is setup by assembler code */
32 32 /* If memory could be changed, we should return the true value here */
33   - return 64*1024*1024;
  33 + return MEM_SIZE*1024*1024;
34 34 }
35 35  
36 36 #define BCSR_PCMCIA_PC0DRVEN 0x0010
... ... @@ -42,8 +42,8 @@
42 42 int checkboard (void)
43 43 {
44 44 u16 status;
45   - volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
46   - volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
  45 + volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
  46 + volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
47 47 volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
48 48 u32 proc_id;
49 49  
... ... @@ -65,6 +65,11 @@
65 65 case 2:
66 66 puts ("Board: DbAu1100\n");
67 67 printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
  68 + (proc_id >> 8) & 0xFF, proc_id & 0xFF);
  69 + break;
  70 + case 3:
  71 + puts ("Board: DbAu1550\n");
  72 + printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
68 73 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
69 74 break;
70 75 default:
board/dbau1x00/memsetup.S
Diff comments   View file @ ff36fd8
... ... @@ -9,7 +9,8 @@
9 9 #define AU1500_SYS_ADDR 0xB1900000
10 10 #define sys_endian 0x0038
11 11 #define CP0_Config0 $16
12   -#define MEM_1MS ((396000000/1000000) * 1000)
  12 +#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
  13 +#define MEM_1MS ((CFG_MHZ) * 1000)
13 14  
14 15 .text
15 16 .set noreorder
... ... @@ -23,6 +24,19 @@
23 24 * Switch S1.1 Off(bit7 reads 1) is Little Endian
24 25 * Switch S1.1 On (bit7 reads 0) is Big Endian
25 26 */
  27 +#ifdef CONFIG_DBAU1550
  28 + li t0, MEM_STCFG2
  29 + li t1, 0x00000040
  30 + sw t1, 0(t0)
  31 +
  32 + li t0, MEM_STTIME2
  33 + li t1, 0x22080a20
  34 + sw t1, 0(t0)
  35 +
  36 + li t0, MEM_STADDR2
  37 + li t1, 0x10c03f00
  38 + sw t1, 0(t0)
  39 +#else
26 40 li t0, MEM_STCFG1
27 41 li t1, 0x00000080
28 42 sw t1, 0(t0)
29 43  
... ... @@ -34,9 +48,10 @@
34 48 li t0, MEM_STADDR1
35 49 li t1, 0x10c03f00
36 50 sw t1, 0(t0)
  51 +#endif
37 52  
38   - li t0, 0xAE000008
39   - lw t1,0(t0)
  53 + li t0, DB1XX0_BCSR_ADDR
  54 + lw t1,8(t0)
40 55 andi t1,t1,0x80
41 56 beq zero,t1,big_endian
42 57 nop
43 58  
... ... @@ -98,10 +113,82 @@
98 113 mtc0 zero, CP0_WIRED
99 114 nop
100 115  
  116 +#ifdef CONFIG_DBAU1550
  117 + /* No workaround if running from ram */
  118 + lui t0, 0xffc0
  119 + lui t3, 0xbfc0
  120 + and t1, ra, t0
  121 + bne t1, t3, noCacheJump
  122 + nop
  123 +
  124 + /*** From AMD YAMON ***/
  125 + /*
  126 + * Step 8) Initialize the caches
  127 + */
  128 + li t0, (16*1024)
  129 + li t1, 32
  130 + li t2, 0x80000000
  131 + addu t3, t0, t2
  132 +cacheloop:
  133 + cache 0, 0(t2)
  134 + cache 1, 0(t2)
  135 + addu t2, t1
  136 + bne t2, t3, cacheloop
  137 + nop
  138 +
  139 + /* Save return address */
  140 + move t3, ra
  141 +
  142 + /* Run from cacheable space now */
  143 + bal cachehere
  144 + nop
  145 +cachehere:
  146 + li t1, ~0x20000000 /* convert to KSEG0 */
  147 + and t0, ra, t1
  148 + addi t0, 5*4 /* 5 insns beyond cachehere */
  149 + jr t0
  150 + nop
  151 +
  152 + /* Restore return address */
  153 + move ra, t3
  154 +
  155 + /*
  156 + * Step 9) Initialize the TLB
  157 + */
  158 + li t0, 0 # index value
  159 + li t1, 0x00000000 # entryhi value
  160 + li t2, 32 # 32 entries
  161 +
  162 +tlbloop:
  163 + /* Probe TLB for matching EntryHi */
  164 + mtc0 t1, CP0_ENTRYHI
  165 + tlbp
  166 + nop
  167 +
  168 + /* Examine Index[P], 1=no matching entry */
  169 + mfc0 t3, CP0_INDEX
  170 + li t4, 0x80000000
  171 + and t3, t4, t3
  172 + addiu t1, t1, 1 # increment t1 (asid)
  173 + beq zero, t3, tlbloop
  174 + nop
  175 +
  176 + /* Initialize the TLB entry */
  177 + mtc0 t0, CP0_INDEX
  178 + mtc0 zero, CP0_ENTRYLO0
  179 + mtc0 zero, CP0_ENTRYLO1
  180 + mtc0 zero, CP0_PAGEMASK
  181 + tlbwi
  182 +
  183 + /* Do it again */
  184 + addiu t0, t0, 1
  185 + bne t0, t2, tlbloop
  186 + nop
  187 +
101 188 /* First setup pll:s to make serial work ok */
102 189 /* We have a 12 MHz crystal */
103 190 li t0, SYS_CPUPLL
104   - li t1, 0x21 /* 396 MHz */
  191 + li t1, CPU_SCALE /* CPU clock */
105 192 sw t1, 0(t0)
106 193 sync
107 194 nop
108 195  
109 196  
110 197  
111 198  
112 199  
113 200  
... ... @@ -119,19 +206,49 @@
119 206 sync
120 207  
121 208 /* Static memory controller */
  209 + /* RCE0 - can not change while fetching, do so from icache */
  210 + move t2, ra /* Store return address */
  211 + bal getAddr
  212 + nop
122 213  
123   - /* RCE0 AMD 29LV640M MirrorBit Flash */
  214 +getAddr:
  215 + move t1, ra
  216 + move ra, t2 /* Move return addess back */
  217 +
  218 + cache 0x14,0(t1)
  219 + cache 0x14,32(t1)
  220 + /*** /From YAMON ***/
  221 +
  222 +noCacheJump:
  223 +#endif /* CONFIG_DBAU1550 */
  224 +
  225 +#ifdef CONFIG_DBAU1550
  226 + li t0, MEM_STTIME0
  227 + li t1, 0x040181D7
  228 + sw t1, 0(t0)
  229 +
  230 + /* RCE0 AMD MirrorBit Flash (?) */
124 231 li t0, MEM_STCFG0
125   - li t1, 0x00000013
  232 + li t1, 0x00000003
126 233 sw t1, 0(t0)
127 234  
  235 + li t0, MEM_STADDR0
  236 + li t1, 0x11803E00
  237 + sw t1, 0(t0)
  238 +#else /* CONFIG_DBAU1550 */
128 239 li t0, MEM_STTIME0
129   - li t1, 0x040181D7
  240 + li t1, 0x00014C0F
130 241 sw t1, 0(t0)
131 242  
  243 + /* RCE0 AMD 29LV640M MirrorBit Flash */
  244 + li t0, MEM_STCFG0
  245 + li t1, 0x00000013
  246 + sw t1, 0(t0)
  247 +
132 248 li t0, MEM_STADDR0
133 249 li t1, 0x11E03F80
134 250 sw t1, 0(t0)
  251 +#endif /* CONFIG_DBAU1550 */
135 252  
136 253 /* RCE1 CPLD Board Logic */
137 254 li t0, MEM_STCFG1
138 255  
... ... @@ -146,8 +263,21 @@
146 263 li t1, 0x10c03f00
147 264 sw t1, 0(t0)
148 265  
  266 +#ifdef CONFIG_DBAU1550
149 267 /* RCE2 CPLD Board Logic */
150 268 li t0, MEM_STCFG2
  269 + li t1, 0x00000040
  270 + sw t1, 0(t0)
  271 +
  272 + li t0, MEM_STTIME2
  273 + li t1, 0x22080a20
  274 + sw t1, 0(t0)
  275 +
  276 + li t0, MEM_STADDR2
  277 + li t1, 0x10c03f00
  278 + sw t1, 0(t0)
  279 +#else
  280 + li t0, MEM_STCFG2
151 281 li t1, 0x00000000
152 282 sw t1, 0(t0)
153 283  
... ... @@ -158,6 +288,7 @@
158 288 li t0, MEM_STADDR2
159 289 li t1, 0x00000000
160 290 sw t1, 0(t0)
  291 +#endif
161 292  
162 293 /* RCE3 PCMCIA 250ns */
163 294 li t0, MEM_STCFG3
... ... @@ -281,6 +412,99 @@
281 412 bne t1, zero, 1b
282 413 nop
283 414  
  415 +#ifdef CONFIG_DBAU1550
  416 +/* SDCS 0,1,2 DDR SDRAM */
  417 + li t0, MEM_SDMODE0
  418 + li t1, 0x04276221
  419 + sw t1, 0(t0)
  420 +
  421 + li t0, MEM_SDMODE1
  422 + li t1, 0x04276221
  423 + sw t1, 0(t0)
  424 +
  425 + li t0, MEM_SDMODE2
  426 + li t1, 0x04276221
  427 + sw t1, 0(t0)
  428 +
  429 + li t0, MEM_SDADDR0
  430 + li t1, 0xe21003f0
  431 + sw t1, 0(t0)
  432 +
  433 + li t0, MEM_SDADDR1
  434 + li t1, 0xe21043f0
  435 + sw t1, 0(t0)
  436 +
  437 + li t0, MEM_SDADDR2
  438 + li t1, 0xe21083f0
  439 + sw t1, 0(t0)
  440 +
  441 + sync
  442 +
  443 + li t0, MEM_SDCONFIGA
  444 + li t1, 0x9030060a /* Program refresh - disabled */
  445 + sw t1, 0(t0)
  446 + sync
  447 +
  448 + li t0, MEM_SDCONFIGB
  449 + li t1, 0x00028000
  450 + sw t1, 0(t0)
  451 + sync
  452 +
  453 + li t0, MEM_SDPRECMD /* Precharge all */
  454 + li t1, 0
  455 + sw t1, 0(t0)
  456 + sync
  457 +
  458 + li t0, MEM_SDWRMD0
  459 + li t1, 0x40000000
  460 + sw t1, 0(t0)
  461 + sync
  462 +
  463 + li t0, MEM_SDWRMD1
  464 + li t1, 0x40000000
  465 + sw t1, 0(t0)
  466 + sync
  467 +
  468 + li t0, MEM_SDWRMD2
  469 + li t1, 0x40000000
  470 + sw t1, 0(t0)
  471 + sync
  472 +
  473 + li t0, MEM_SDWRMD0
  474 + li t1, 0x00000063
  475 + sw t1, 0(t0)
  476 + sync
  477 +
  478 + li t0, MEM_SDWRMD1
  479 + li t1, 0x00000063
  480 + sw t1, 0(t0)
  481 + sync
  482 +
  483 + li t0, MEM_SDWRMD2
  484 + li t1, 0x00000063
  485 + sw t1, 0(t0)
  486 + sync
  487 +
  488 + li t0, MEM_SDPRECMD /* Precharge all */
  489 + sw zero, 0(t0)
  490 + sync
  491 +
  492 + /* Issue 2 autoref */
  493 + li t0, MEM_SDAUTOREF
  494 + sw zero, 0(t0)
  495 + sync
  496 +
  497 + li t0, MEM_SDAUTOREF
  498 + sw zero, 0(t0)
  499 + sync
  500 +
  501 + /* Enable refresh */
  502 + li t0, MEM_SDCONFIGA
  503 + li t1, 0x9830060a /* Program refresh - enabled */
  504 + sw t1, 0(t0)
  505 + sync
  506 +
  507 +#else /* CONFIG_DBAU1550 */
284 508 /* SDCS 0,1 SDRAM */
285 509 li t0, MEM_SDMODE0
286 510 li t1, 0x005522AA
... ... @@ -339,6 +563,7 @@
339 563 sw t1, 0(t0)
340 564 sync
341 565  
  566 +#endif /* CONFIG_DBAU1550 */
342 567 /* wait 1mS after setup */
343 568 li t1, MEM_1MS
344 569 1: add t1, -1
... ... @@ -38,6 +38,9 @@
38 38 #elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
39 39 || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
40 40 return &serial_scc_device;
  41 +#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
  42 + || defined(CONFIG_405EP)
  43 + return &serial0_device;
41 44 #else
42 45 #error No default console
43 46 #endif
... ... @@ -69,6 +72,12 @@
69 72 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
70 73 || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
71 74 serial_register (&serial_scc_device);
  75 +#endif
  76 +
  77 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
  78 + || defined(CONFIG_405EP)
  79 + serial_register(&serial0_device);
  80 + serial_register(&serial1_device);
72 81 #endif
73 82  
74 83 serial_assign (default_serial_console ()->name);
cpu/mips/au1x00_eth.c
Diff comments   View file @ ff36fd8
... ... @@ -46,7 +46,12 @@
46 46 #define ETH0_BASE AU1500_ETH0_BASE
47 47 #define MAC0_ENABLE AU1500_MAC0_ENABLE
48 48 #else
  49 +#ifdef CONFIG_AU1550
  50 +#define ETH0_BASE AU1550_ETH0_BASE
  51 +#define MAC0_ENABLE AU1550_MAC0_ENABLE
  52 +#else
49 53 #error "No valid cpu set"
  54 +#endif
50 55 #endif
51 56 #endif
52 57 #endif
cpu/mips/au1x00_serial.c
Diff comments   View file @ ff36fd8
... ... @@ -71,8 +71,8 @@
71 71 volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
72 72 volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
73 73  
74   - /* Set baudrate to 115200 */
75   - *uart_clk = 0x36;
  74 + /* Set baudrate - FIXME for bus speeds != CPU/2 */
  75 + *uart_clk = ((CFG_HZ/(CONFIG_BAUDRATE * 64)));
76 76  
77 77 /* Set parity, stop bits and word length to 8N1 */
78 78 *uart_lcr = UART_LCR_WLEN8;
... ... @@ -41,13 +41,20 @@
41 41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
42 42 */
43 43 /*------------------------------------------------------------------------------- */
44   -
  44 +/*
  45 + * Travis Sawyer 15 September 2004
  46 + * Added CONFIG_SERIAL_MULTI support
  47 + */
45 48 #include <common.h>
46 49 #include <commproc.h>
47 50 #include <asm/processor.h>
48 51 #include <watchdog.h>
49 52 #include "vecnum.h"
50 53  
  54 +#ifdef CONFIG_SERIAL_MULTI
  55 +#include <serial.h>
  56 +#endif
  57 +
51 58 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
52 59 #include <malloc.h>
53 60 #endif
... ... @@ -147,7 +154,6 @@
147 154 #define asyncXOFFchar 0x13
148 155 #define asyncXONchar 0x11
149 156  
150   -
151 157 /*
152 158 * Minimal serial functions needed to use one of the SMC ports
153 159 * as serial console interface.
... ... @@ -177,7 +183,6 @@
177 183 return (0);
178 184 }
179 185  
180   -
181 186 void serial_setbrg (void)
182 187 {
183 188 DECLARE_GLOBAL_DATA_PTR;
... ... @@ -190,7 +195,6 @@
190 195 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
191 196 }
192 197  
193   -
194 198 void serial_putc (const char c)
195 199 {
196 200 if (c == '\n')
... ... @@ -208,7 +212,6 @@
208 212 }
209 213 }
210 214  
211   -
212 215 void serial_puts (const char *s)
213 216 {
214 217 while (*s) {
... ... @@ -216,7 +219,6 @@
216 219 }
217 220 }
218 221  
219   -
220 222 int serial_getc ()
221 223 {
222 224 unsigned char status = 0;
... ... @@ -240,7 +242,6 @@
240 242 return (0x000000ff & (int) in8 (asyncRxBufferport1));
241 243 }
242 244  
243   -
244 245 int serial_tstc ()
245 246 {
246 247 unsigned char status;
... ... @@ -264,7 +265,6 @@
264 265  
265 266 #endif /* CONFIG_IOP480 */
266 267  
267   -
268 268 /*****************************************************************************/
269 269 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
270 270  
... ... @@ -350,7 +350,6 @@
350 350 /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
351 351 /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
352 352  
353   -
354 353 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
355 354 /*-----------------------------------------------------------------------------+
356 355 | Fifo
... ... @@ -364,7 +363,6 @@
364 363 volatile static serial_buffer_t buf_info;
365 364 #endif
366 365  
367   -
368 366 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
369 367 static void serial_divs (int baudrate, unsigned long *pudiv,
370 368 unsigned short *pbdiv )
371 369  
... ... @@ -411,14 +409,17 @@
411 409 }
412 410 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
413 411  
414   -
415 412 /*
416 413 * Minimal serial functions needed to use one of the SMC ports
417 414 * as serial console interface.
418 415 */
419 416  
420 417 #if defined(CONFIG_440)
421   -int serial_init (void)
  418 +#if defined(CONFIG_SERIAL_MULTI)
  419 +int serial_init_dev (unsigned long dev_base)
  420 +#else
  421 +int serial_init(void)
  422 +#endif
422 423 {
423 424 DECLARE_GLOBAL_DATA_PTR;
424 425  
425 426  
... ... @@ -431,8 +432,18 @@
431 432 #endif
432 433  
433 434 #if defined(CONFIG_440_GX)
  435 +#if defined(CONFIG_SERIAL_MULTI)
  436 + if (UART0_BASE == dev_base) {
  437 + mfsdr(UART0_SDR,reg);
  438 + reg &= ~CR0_MASK;
  439 + } else {
  440 + mfsdr(UART1_SDR,reg);
  441 + reg &= ~CR0_MASK;
  442 + }
  443 +#else
434 444 mfsdr(UART0_SDR,reg);
435 445 reg &= ~CR0_MASK;
  446 +#endif
436 447 #else
437 448 reg = mfdcr(cntrl0) & ~CR0_MASK;
438 449 #endif /* CONFIG_440_GX */
439 450  
440 451  
... ... @@ -451,11 +462,32 @@
451 462  
452 463 #if defined(CONFIG_440_GX)
453 464 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
  465 +#if defined(CONFIG_SERIAL_MULTI)
  466 + if (UART0_BASE == dev_base) {
  467 + mtsdr (UART0_SDR,reg);
  468 + } else {
  469 + mtsdr (UART1_SDR,reg);
  470 + }
  471 +#else
454 472 mtsdr (UART0_SDR,reg);
  473 +#endif
455 474 #else
456 475 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
457 476 mtdcr (cntrl0, reg);
458 477 #endif
  478 +
  479 +#if defined(CONFIG_SERIAL_MULTI)
  480 + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
  481 + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
  482 + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  483 + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  484 + out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
  485 + out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
  486 + val = in8 (dev_base + UART_LSR); /* clear line status */
  487 + val = in8 (dev_base + UART_RBR); /* read receive buffer */
  488 + out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
  489 + out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
  490 +#else
459 491 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
460 492 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
461 493 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
462 494  
463 495  
... ... @@ -466,13 +498,17 @@
466 498 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
467 499 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
468 500 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
469   -
  501 +#endif
470 502 return (0);
471 503 }
472 504  
473 505 #else /* !defined(CONFIG_440) */
474 506  
  507 +#if defined(CONFIG_SERIAL_MULTI)
  508 +int serial_init_dev (unsigned long dev_base)
  509 +#else
475 510 int serial_init (void)
  511 +#endif
476 512 {
477 513 DECLARE_GLOBAL_DATA_PTR;
478 514  
... ... @@ -517,6 +553,18 @@
517 553 tmp = gd->baudrate * udiv * 16;
518 554 bdiv = (clk + tmp / 2) / tmp;
519 555  
  556 +#if defined(CONFIG_SERIAL_MULTI)
  557 + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
  558 + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
  559 + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  560 + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  561 + out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
  562 + out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
  563 + val = in8 (dev_base + UART_LSR); /* clear line status */
  564 + val = in8 (dev_base + UART_RBR); /* read receive buffer */
  565 + out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
  566 + out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
  567 +#else
520 568 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
521 569 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
522 570 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
523 571  
524 572  
... ... @@ -527,13 +575,17 @@
527 575 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
528 576 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
529 577 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
530   -
  578 +#endif
531 579 return (0);
532 580 }
533 581  
534 582 #endif /* if defined(CONFIG_440) */
535 583  
  584 +#if defined(CONFIG_SERIAL_MULTI)
  585 +void serial_setbrg_dev (unsigned long dev_base)
  586 +#else
536 587 void serial_setbrg (void)
  588 +#endif
537 589 {
538 590 DECLARE_GLOBAL_DATA_PTR;
539 591  
540 592  
541 593  
542 594  
543 595  
544 596  
545 597  
546 598  
547 599  
548 600  
549 601  
550 602  
551 603  
552 604  
553 605  
... ... @@ -556,39 +608,71 @@
556 608 tmp = gd->baudrate * udiv * 16;
557 609 bdiv = (clk + tmp / 2) / tmp;
558 610  
  611 +#if defined(CONFIG_SERIAL_MULTI)
  612 + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
  613 + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
  614 + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  615 + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  616 +#else
559 617 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
560 618 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
561 619 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
562 620 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  621 +#endif
563 622 }
564 623  
565   -
  624 +#if defined(CONFIG_SERIAL_MULTI)
  625 +void serial_putc_dev (unsigned long dev_base, const char c)
  626 +#else
566 627 void serial_putc (const char c)
  628 +#endif
567 629 {
568 630 int i;
569 631  
570 632 if (c == '\n')
  633 +#if defined(CONFIG_SERIAL_MULTI)
  634 + serial_putc_dev (dev_base, '\r');
  635 +#else
571 636 serial_putc ('\r');
  637 +#endif
572 638  
573 639 /* check THRE bit, wait for transmiter available */
574 640 for (i = 1; i < 3500; i++) {
  641 +#if defined(CONFIG_SERIAL_MULTI)
  642 + if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
  643 +#else
575 644 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
  645 +#endif
576 646 break;
577 647 udelay (100);
578 648 }
  649 +#if defined(CONFIG_SERIAL_MULTI)
  650 + out8 (dev_base + UART_THR, c); /* put character out */
  651 +#else
579 652 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
  653 +#endif
580 654 }
581 655  
582   -
  656 +#if defined(CONFIG_SERIAL_MULTI)
  657 +void serial_puts_dev (unsigned long dev_base, const char *s)
  658 +#else
583 659 void serial_puts (const char *s)
  660 +#endif
584 661 {
585 662 while (*s) {
  663 +#if defined(CONFIG_SERIAL_MULTI)
  664 + serial_putc_dev (dev_base, *s++);
  665 +#else
586 666 serial_putc (*s++);
  667 +#endif
587 668 }
588 669 }
589 670  
590   -
591   -int serial_getc ()
  671 +#if defined(CONFIG_SERIAL_MULTI)
  672 +int serial_getc_dev (unsigned long dev_base)
  673 +#else
  674 +int serial_getc (void)
  675 +#endif
592 676 {
593 677 unsigned char status = 0;
594 678  
595 679  
... ... @@ -596,7 +680,11 @@
596 680 #if defined(CONFIG_HW_WATCHDOG)
597 681 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
598 682 #endif /* CONFIG_HW_WATCHDOG */
  683 +#if defined(CONFIG_SERIAL_MULTI)
  684 + status = in8 (dev_base + UART_LSR);
  685 +#else
599 686 status = in8 (ACTING_UART0_BASE + UART_LSR);
  687 +#endif
600 688 if ((status & asyncLSRDataReady1) != 0x0) {
601 689 break;
602 690 }
603 691  
604 692  
605 693  
606 694  
607 695  
608 696  
... ... @@ -604,22 +692,37 @@
604 692 asyncLSROverrunError1 |
605 693 asyncLSRParityError1 |
606 694 asyncLSRBreakInterrupt1 )) != 0) {
  695 +#if defined(CONFIG_SERIAL_MULTI)
  696 + out8 (dev_base + UART_LSR,
  697 +#else
607 698 out8 (ACTING_UART0_BASE + UART_LSR,
  699 +#endif
608 700 asyncLSRFramingError1 |
609 701 asyncLSROverrunError1 |
610 702 asyncLSRParityError1 |
611 703 asyncLSRBreakInterrupt1);
612 704 }
613 705 }
  706 +#if defined(CONFIG_SERIAL_MULTI)
  707 + return (0x000000ff & (int) in8 (dev_base));
  708 +#else
614 709 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
  710 +#endif
615 711 }
616 712  
617   -
618   -int serial_tstc ()
  713 +#if defined(CONFIG_SERIAL_MULTI)
  714 +int serial_tstc_dev (unsigned long dev_base)
  715 +#else
  716 +int serial_tstc (void)
  717 +#endif
619 718 {
620 719 unsigned char status;
621 720  
  721 +#if defined(CONFIG_SERIAL_MULTI)
  722 + status = in8 (dev_base + UART_LSR);
  723 +#else
622 724 status = in8 (ACTING_UART0_BASE + UART_LSR);
  725 +#endif
623 726 if ((status & asyncLSRDataReady1) != 0x0) {
624 727 return (1);
625 728 }
626 729  
... ... @@ -627,7 +730,11 @@
627 730 asyncLSROverrunError1 |
628 731 asyncLSRParityError1 |
629 732 asyncLSRBreakInterrupt1 )) != 0) {
  733 +#if defined(CONFIG_SERIAL_MULTI)
  734 + out8 (dev_base + UART_LSR,
  735 +#else
630 736 out8 (ACTING_UART0_BASE + UART_LSR,
  737 +#endif
631 738 asyncLSRFramingError1 |
632 739 asyncLSROverrunError1 |
633 740 asyncLSRParityError1 |
... ... @@ -636,7 +743,6 @@
636 743 return 0;
637 744 }
638 745  
639   -
640 746 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
641 747  
642 748 void serial_isr (void *arg)
... ... @@ -651,8 +757,8 @@
651 757 } else {
652 758 space = rx_get - rx_put;
653 759 }
654   - while (serial_tstc ()) {
655   - c = serial_getc ();
  760 + while (serial_tstc_dev (ACTING_UART0_BASE)) {
  761 + c = serial_getc_dev (ACTING_UART0_BASE);
656 762 if (space) {
657 763 buf_info.rx_buffer[rx_put++] = c;
658 764 space--;
... ... @@ -752,7 +858,6 @@
752 858  
753 859 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
754 860  
755   -
756 861 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
757 862 /*
758 863 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
... ... @@ -788,7 +893,6 @@
788 893 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
789 894 }
790 895  
791   -
792 896 void putDebugChar (const char c)
793 897 {
794 898 if (c == '\n')
... ... @@ -800,7 +904,6 @@
800 904 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
801 905 }
802 906  
803   -
804 907 void putDebugStr (const char *s)
805 908 {
806 909 while (*s) {
... ... @@ -808,7 +911,6 @@
808 911 }
809 912 }
810 913  
811   -
812 914 int getDebugChar (void)
813 915 {
814 916 unsigned char status = 0;
... ... @@ -832,7 +934,6 @@
832 934 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
833 935 }
834 936  
835   -
836 937 void kgdb_interruptible (int yes)
837 938 {
838 939 return;
... ... @@ -866,6 +967,89 @@
866 967 }
867 968 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
868 969 #endif /* CFG_CMD_KGDB */
  970 +
  971 +
  972 +#if defined(CONFIG_SERIAL_MULTI)
  973 +int serial0_init(void)
  974 +{
  975 + return (serial_init_dev(UART0_BASE));
  976 +}
  977 +
  978 +int serial1_init(void)
  979 +{
  980 + return (serial_init_dev(UART1_BASE));
  981 +}
  982 +void serial0_setbrg (void)
  983 +{
  984 + serial_setbrg_dev(UART0_BASE);
  985 +}
  986 +void serial1_setbrg (void)
  987 +{
  988 + serial_setbrg_dev(UART1_BASE);
  989 +}
  990 +
  991 +void serial0_putc(const char c)
  992 +{
  993 + serial_putc_dev(UART0_BASE,c);
  994 +}
  995 +
  996 +void serial1_putc(const char c)
  997 +{
  998 + serial_putc_dev(UART1_BASE, c);
  999 +}
  1000 +void serial0_puts(const char *s)
  1001 +{
  1002 + serial_puts_dev(UART0_BASE, s);
  1003 +}
  1004 +
  1005 +void serial1_puts(const char *s)
  1006 +{
  1007 + serial_puts_dev(UART1_BASE, s);
  1008 +}
  1009 +
  1010 +int serial0_getc(void)
  1011 +{
  1012 + return(serial_getc_dev(UART0_BASE));
  1013 +}
  1014 +
  1015 +int serial1_getc(void)
  1016 +{
  1017 + return(serial_getc_dev(UART1_BASE));
  1018 +}
  1019 +int serial0_tstc(void)
  1020 +{
  1021 + return (serial_tstc_dev(UART0_BASE));
  1022 +}
  1023 +
  1024 +int serial1_tstc(void)
  1025 +{
  1026 + return (serial_tstc_dev(UART1_BASE));
  1027 +}
  1028 +
  1029 +struct serial_device serial0_device =
  1030 +{
  1031 + "serial0",
  1032 + "UART0",
  1033 + serial0_init,
  1034 + serial0_setbrg,
  1035 + serial0_getc,
  1036 + serial0_tstc,
  1037 + serial0_putc,
  1038 + serial0_puts,
  1039 +};
  1040 +
  1041 +struct serial_device serial1_device =
  1042 +{
  1043 + "serial1",
  1044 + "UART1",
  1045 + serial1_init,
  1046 + serial1_setbrg,
  1047 + serial1_getc,
  1048 + serial1_tstc,
  1049 + serial1_putc,
  1050 + serial1_puts,
  1051 +};
  1052 +#endif /* CONFIG_SERIAL_MULTI */
869 1053  
870 1054 #endif /* CONFIG_405GP || CONFIG_405CR */
doc/README.serial_multi
Diff comments   View file @ ff36fd8
... ... @@ -2,6 +2,8 @@
2 2 intended to allow for modem dial-in / dial-out while still being able
3 3 to use a serial console on a (different) serial port.
4 4  
  5 +MPC8XX Specific
  6 +===============
5 7 At the moment, the ports must be split on a SMC and a SCC port on a
6 8 8xx processor; other configurations are not (yet) supported.
7 9  
... ... @@ -35,4 +37,19 @@
35 37 After that press 'enter' at the SCC console. Note that baudrates <38400
36 38 are not allowed on LWMON with watchdog enabled (see CFG_BAUDRATE_TABLE in
37 39 include/configs/lwmon.h).
  40 +
  41 +
  42 +PPC4XX Specific
  43 +===============
  44 +*) The default console is UART0
  45 +
  46 +*) The console can be switched to UART1 by any of the following commands:
  47 + setenv stdout serial1
  48 + setenv stderr serial1
  49 + setenv stdin serial1
  50 +
  51 +*) The console can be switched to UART0 by any of the following commands:
  52 + setenv stdout serial0
  53 + setenv stderr serial0
  54 + setenv stdin serial0
include/asm-mips/au1x00.h
Diff comments   View file @ ff36fd8
... ... @@ -132,6 +132,27 @@
132 132 #define CP0_DEBUG $23
133 133  
134 134 /* SDRAM Controller */
  135 +#ifdef CONFIG_AU1550
  136 +
  137 +#define MEM_SDMODE0 0xB4000800
  138 +#define MEM_SDMODE1 0xB4000808
  139 +#define MEM_SDMODE2 0xB4000810
  140 +
  141 +#define MEM_SDADDR0 0xB4000820
  142 +#define MEM_SDADDR1 0xB4000828
  143 +#define MEM_SDADDR2 0xB4000830
  144 +
  145 +#define MEM_SDCONFIGA 0xB4000840
  146 +#define MEM_SDCONFIGB 0xB4000848
  147 +#define MEM_SDPRECMD 0xB40008c0
  148 +#define MEM_SDAUTOREF 0xB40008c8
  149 +
  150 +#define MEM_SDWRMD0 0xB4000880
  151 +#define MEM_SDWRMD1 0xB4000888
  152 +#define MEM_SDWRMD2 0xB4000890
  153 +
  154 +#else /* CONFIG_AU1550 */
  155 +
135 156 #define MEM_SDMODE0 0xB4000000
136 157 #define MEM_SDMODE1 0xB4000004
137 158 #define MEM_SDMODE2 0xB4000008
... ... @@ -148,6 +169,8 @@
148 169 #define MEM_SDWRMD1 0xB4000028
149 170 #define MEM_SDWRMD2 0xB400002C
150 171  
  172 +#endif /* CONFIG_AU1550 */
  173 +
151 174 #define MEM_SDSLEEP 0xB4000030
152 175 #define MEM_SDSMCKE 0xB4000034
153 176  
... ... @@ -474,6 +497,8 @@
474 497 #define AU1500_ETH0_BASE 0xB1500000
475 498 #define AU1500_ETH1_BASE 0xB1510000
476 499 #define AU1100_ETH0_BASE 0xB0500000
  500 +#define AU1550_ETH0_BASE 0xB0500000
  501 +#define AU1550_ETH1_BASE 0xB0510000
477 502  
478 503 /* 4 byte offsets from AU1000_ETH_BASE */
479 504 #define MAC_CONTROL 0x0
... ... @@ -523,6 +548,8 @@
523 548 #define AU1500_MAC0_ENABLE 0xB1520000
524 549 #define AU1500_MAC1_ENABLE 0xB1520004
525 550 #define AU1100_MAC0_ENABLE 0xB0520000
  551 +#define AU1550_MAC0_ENABLE 0xB0520000
  552 +#define AU1550_MAC1_ENABLE 0xB0520004
526 553  
527 554 #define MAC_EN_CLOCK_ENABLE (1<<0)
528 555 #define MAC_EN_RESET0 (1<<1)
... ... @@ -978,6 +1005,15 @@
978 1005 #define AC97C_CNTRL 0xB0000010
979 1006 #define AC97C_RS (1<<1)
980 1007 #define AC97C_CE (1<<0)
  1008 +
  1009 +#define DB1000_BCSR_ADDR 0xAE000000
  1010 +#define DB1550_BCSR_ADDR 0xAF000000
  1011 +
  1012 +#ifdef CONFIG_DBAU1550
  1013 +#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
  1014 +#else
  1015 +#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
  1016 +#endif
981 1017  
982 1018 #ifdef CONFIG_SOC_AU1500
983 1019 /* Au1500 PCI Controller */
include/configs/dbau1x00.h
Diff comments   View file @ ff36fd8
... ... @@ -42,10 +42,15 @@
42 42 #ifdef CONFIG_DBAU1500
43 43 #define CONFIG_AU1500 1
44 44 #else
  45 +#ifdef CONFIG_DBAU1550
  46 +/* Cabernet */
  47 +#define CONFIG_AU1550 1
  48 +#else
45 49 #error "No valid board set"
46 50 #endif
47 51 #endif
48 52 #endif
  53 +#endif
49 54  
50 55 #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
51 56  
52 57  
53 58  
... ... @@ -66,23 +71,34 @@
66 71 "bootfile=/tftpboot/vmlinux.srec\0" \
67 72 "load=tftp 80500000 $(u-boot)\0" \
68 73 ""
  74 +
  75 +#ifdef CONFIG_DBAU1550
  76 +/* Boot from flash by default, revert to bootp */
  77 +#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
  78 +
  79 +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \
  80 + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
  81 + CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
  82 + CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
  83 +#else /* CONFIG_DBAU1550 */
69 84 /* Boot from Compact flash partition 2 as default */
70 85 #define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm"
71 86  
72   -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
73   - CFG_CMD_IDE | \
74   - CFG_CMD_DHCP | \
75   - CFG_CMD_ELF ) & \
76   - ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
77   - CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
78   - CFG_CMD_BDI | CFG_CMD_BEDBUG))
  87 +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
  88 + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
  89 + CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \
  90 + CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG))
  91 +#endif /* CONFIG_DBAU1550 */
  92 +
79 93 #include <cmd_confdefs.h>
80 94  
81 95 /*
82 96 * Miscellaneous configurable options
83 97 */
84 98 #define CFG_LONGHELP /* undef to save memory */
85   -#define CFG_PROMPT "DbAu1x00 # " /* Monitor Command Prompt */
  99 +
  100 +#define CFG_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
  101 +
86 102 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
87 103 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
88 104 #define CFG_MAXARGS 16 /* max number of command args*/
89 105  
... ... @@ -91,8 +107,14 @@
91 107  
92 108 #define CFG_BOOTPARAMS_LEN 128*1024
93 109  
94   -#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */
  110 +#define CFG_MHZ 396
95 111  
  112 +#if (CFG_MHZ % 12) != 0
  113 +#error "Invalid CPU frequency - must be multiple of 12!"
  114 +#endif
  115 +
  116 +#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
  117 +
96 118 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
97 119  
98 120 #define CFG_LOAD_ADDR 0x81000000 /* default load address */
99 121  
100 122  
... ... @@ -103,12 +125,29 @@
103 125 /*-----------------------------------------------------------------------
104 126 * FLASH and environment organization
105 127 */
  128 +#ifdef CONFIG_DBAU1550
  129 +
106 130 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  131 +#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
  132 +
  133 +#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
  134 +#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
  135 +
  136 +#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
  137 +
  138 +#else /* CONFIG_DBAU1550 */
  139 +
  140 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
107 141 #define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
108 142  
109 143 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
110 144 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
111 145  
  146 +#endif /* CONFIG_DBAU1550 */
  147 +
  148 +#define CFG_FLASH_CFI 1
  149 +#define CFG_FLASH_CFI_DRIVER 1
  150 +
112 151 /* The following #defines are needed to get flash environment right */
113 152 #define CFG_MONITOR_BASE TEXT_BASE
114 153 #define CFG_MONITOR_LEN (192 << 10)
115 154  
... ... @@ -134,8 +173,15 @@
134 173  
135 174 #define CONFIG_NET_MULTI
136 175  
  176 +#ifdef CONFIG_DBAU1550
  177 +#define MEM_SIZE 192
  178 +#else
  179 +#define MEM_SIZE 64
  180 +#endif
  181 +
137 182 #define CONFIG_MEMSIZE_IN_BYTES
138 183  
  184 +#ifndef CONFIG_DBAU1550
139 185 /*---ATA PCMCIA ------------------------------------*/
140 186 #define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
141 187 #define CFG_PCMCIA_MEM_ADDR 0x20000000
... ... @@ -166,6 +212,7 @@
166 212  
167 213 /* Offset for alternate registers */
168 214 #define CFG_ATA_ALT_OFFSET 0x0100
  215 +#endif /* CONFIG_DBAU1550 */
169 216  
170 217 /*-----------------------------------------------------------------------
171 218 * Cache Configuration
... ... @@ -173,8 +220,6 @@
173 220 #define CFG_DCACHE_SIZE 16384
174 221 #define CFG_ICACHE_SIZE 16384
175 222 #define CFG_CACHELINE_SIZE 32
176   -
177   -#define DB1000_BCSR_ADDR 0xAE000000
178 223  
179 224 #endif /* __CONFIG_H */
... ... @@ -22,6 +22,13 @@
22 22 extern struct serial_device serial_scc_device;
23 23 extern struct serial_device * default_serial_console (void);
24 24  
  25 +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
  26 + || defined(CONFIG_405EP)
  27 +extern struct serial_device serial0_device;
  28 +extern struct serial_device serial1_device;
  29 +#endif
  30 +
  31 +
25 32 extern void serial_initialize(void);
26 33 extern void serial_devices_init(void);
27 34 extern int serial_assign(char * name);