armv8: ls1012a: Add support of ls1012afrdm board

QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>

armv8: ls1012a: Add support of ls1012afrdm board
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Prabhakar Kushwaha · York Sun
1 parent 3b6e3898c2
Showing 11 changed files with 416 additions and 1 deletions Side-by-side Diff
arch/arm/Kconfig
arch/arm/dts/Makefile
arch/arm/dts/fsl-ls1012a-frdm.dts
arch/arm/dts/fsl-ls1012a-frdm.dtsi
board/freescale/ls1012afrdm/Kconfig
board/freescale/ls1012afrdm/MAINTAINERS
board/freescale/ls1012afrdm/Makefile
board/freescale/ls1012afrdm/README
board/freescale/ls1012afrdm/ls1012afrdm.c
configs/ls1012afrdm_qspi_defconfig
include/configs/ls1012afrdm.h
@@ -714,6 +714,15 @@
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
  
+config TARGET_LS1012AFRDM
+	bool "Support ls1012afrdm"
+	select ARM64
+	help
+	  Support for Freescale LS1012AFRDM platform.
+	  The LS1012A Freedom  board (FRDM) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -872,6 +881,7 @@
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
@@ -122,7 +122,8 @@
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
 	fsl-ls1012a-qds.dtb \
-	fsl-ls1012a-rdb.dtb
+	fsl-ls1012a-rdb.dtb \
+	fsl-ls1012a-frdm.dtb
  
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
  
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &duart0;
+	};
+};
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A FREEDOM Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+	default "ls1012afrdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012afrdm"
+
+endif
+LS1012AFRDM BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012afrdm/
+F:	include/configs/ls1012afrdm.h
+F:	configs/ls1012afrdm_qspi_defconfig
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+     - 2 SGMII 1G PHYs
+ - DDR Controller
+     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+	operating at 1.35 V
+ - QSPI
+     - Onboard 512 Mbit QSPI flash memory running at speed up
+      to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+       Micro-AB connector.
+     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+       as a Micro-AB device.
+ - I2C controller
+     - One I2C bus with connectivity to Arduino headers
+ - UART
+     - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+     - ARM Cortex® 10-pin JTAG connector for LS1012A
+     - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+     - One SAI port, SAI 2 with full duplex support
+ - Clocks
+     - 25 MHz crystal for LS1012A
+     - 8 MHz Crystal for K20
+     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+     - 5 V input supply from USB
+     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+       other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	puts("Board: LS1012AFRDM ");
+
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x04180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x84180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
...	...	@@ -714,6 +714,15 @@
714	714	development platform that supports the QorIQ LS1012A
715	715	Layerscape Architecture processor.
716	716
	717	+config TARGET_LS1012AFRDM
	718	+ bool "Support ls1012afrdm"
	719	+ select ARM64
	720	+ help
	721	+ Support for Freescale LS1012AFRDM platform.
	722	+ The LS1012A Freedom board (FRDM) is a high-performance
	723	+ development platform that supports the QorIQ LS1012A
	724	+ Layerscape Architecture processor.
	725	+
717	726	config TARGET_LS1021AQDS
718	727	bool "Support ls1021aqds"
719	728	select CPU_V7
...	...	@@ -872,6 +881,7 @@
872	881	source "board/freescale/ls1043ardb/Kconfig"
873	882	source "board/freescale/ls1012aqds/Kconfig"
874	883	source "board/freescale/ls1012ardb/Kconfig"
	884	+source "board/freescale/ls1012afrdm/Kconfig"
875	885	source "board/freescale/mx23evk/Kconfig"
876	886	source "board/freescale/mx25pdk/Kconfig"
877	887	source "board/freescale/mx28evk/Kconfig"
...	...	@@ -122,7 +122,8 @@
122	122	fsl-ls1043a-qds-lpuart.dtb \
123	123	fsl-ls1043a-rdb.dtb \
124	124	fsl-ls1012a-qds.dtb \
125		- fsl-ls1012a-rdb.dtb
	125	+ fsl-ls1012a-rdb.dtb \
	126	+ fsl-ls1012a-frdm.dtb
126	127
127	128	dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
128	129
	1	+/*
	2	+ * Device Tree file for Freescale Layerscape-1012A family SoC.
	3	+ *
	4	+ * Copyright 2016, Freescale Semiconductor
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+/dts-v1/;
	10	+#include "fsl-ls1012a-frdm.dtsi"
	11	+
	12	+/ {
	13	+ chosen {
	14	+ stdout-path = &duart0;
	15	+ };
	16	+};
	1	+if TARGET_LS1012AFRDM
	2	+
	3	+config SYS_BOARD
	4	+ default "ls1012afrdm"
	5	+
	6	+config SYS_VENDOR
	7	+ default "freescale"
	8	+
	9	+config SYS_SOC
	10	+ default "fsl-layerscape"
	11	+
	12	+config SYS_CONFIG_NAME
	13	+ default "ls1012afrdm"
	14	+
	15	+endif
	1	+LS1012AFRDM BOARD
	2	+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
	3	+S: Maintained
	4	+F: board/freescale/ls1012afrdm/
	5	+F: include/configs/ls1012afrdm.h
	6	+F: configs/ls1012afrdm_qspi_defconfig
	1	+#
	2	+# Copyright 2016 Freescale Semiconductor, Inc.
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y += ls1012afrdm.o
	1	+Overview
	2	+--------
	3	+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
	4	+platform, with a complete debugging environment. The LS1012AFRDM board
	5	+supports the QorIQ LS1012A processor and is optimized to support the
	6	+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
	7	+
	8	+LS1012A SoC Overview
	9	+--------------------
	10	+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
	11	+SoC overview.
	12	+
	13	+ LS1012AFRDM board Overview
	14	+ -----------------------
	15	+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
	16	+ - 2 SGMII 1G PHYs
	17	+ - DDR Controller
	18	+ - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
	19	+ operating at 1.35 V
	20	+ - QSPI
	21	+ - Onboard 512 Mbit QSPI flash memory running at speed up
	22	+ to 108/54 MHz
	23	+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
	24	+ - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
	25	+ Micro-AB connector.
	26	+ - USB 2.0 port is a debug port (CMSIS DAP) and is configured
	27	+ as a Micro-AB device.
	28	+ - I2C controller
	29	+ - One I2C bus with connectivity to Arduino headers
	30	+ - UART
	31	+ - UART (Console): UART1 (Without flow control) for console
	32	+ - ARM JTAG support
	33	+ - ARM Cortex® 10-pin JTAG connector for LS1012A
	34	+ - CMSIS DAP through K20 microcontroller
	35	+ - SAI Audio interface
	36	+ - One SAI port, SAI 2 with full duplex support
	37	+ - Clocks
	38	+ - 25 MHz crystal for LS1012A
	39	+ - 8 MHz Crystal for K20
	40	+ - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
	41	+ - Power Supplies
	42	+ - 5 V input supply from USB
	43	+ - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
	44	+ other board interfaces
	45	+
	46	+Booting Options
	47	+---------------
	48	+QSPI Flash 1
	49	+
	50	+QSPI flash map
	51	+--------------
	52	+Images \| Size \|QSPI Flash Address
	53	+------------------------------------------
	54	+RCW + PBI \| 1MB \| 0x4000_0000
	55	+U-boot \| 1MB \| 0x4010_0000
	56	+U-boot Env \| 1MB \| 0x4020_0000
	57	+PPA FIT image \| 2MB \| 0x4050_0000
	58	+Linux ITB \| ~53MB \| 0x40A0_0000
	1	+/*
	2	+ * Copyright 2016 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <i2c.h>
	9	+#include <asm/io.h>
	10	+#include <asm/arch/clock.h>
	11	+#include <asm/arch/fsl_serdes.h>
	12	+#include <asm/arch/soc.h>
	13	+#include <hwconfig.h>
	14	+#include <fsl_csu.h>
	15	+#include <environment.h>
	16	+#include <fsl_mmdc.h>
	17	+#include <netdev.h>
	18	+
	19	+DECLARE_GLOBAL_DATA_PTR;
	20	+
	21	+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
	22	+{
	23	+ int timeout = 1000;
	24	+
	25	+ out_be32(ptr, value);
	26	+
	27	+ while (in_be32(ptr) & bits) {
	28	+ udelay(100);
	29	+ timeout--;
	30	+ }
	31	+ if (timeout <= 0)
	32	+ puts("Error: wait for clear timeout.\n");
	33	+}
	34	+
	35	+int checkboard(void)
	36	+{
	37	+ puts("Board: LS1012AFRDM ");
	38	+
	39	+ return 0;
	40	+}
	41	+
	42	+void mmdc_init(void)
	43	+{
	44	+ struct mmdc_p_regs *mmdc =
	45	+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
	46	+
	47	+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
	48	+
	49	+ /* configure timing parms */
	50	+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
	51	+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
	52	+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
	53	+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
	54	+
	55	+ /* other parms */
	56	+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
	57	+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
	58	+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
	59	+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
	60	+
	61	+ /* out of reset delays */
	62	+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
	63	+
	64	+ /* physical parms */
	65	+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
	66	+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
	67	+
	68	+ /* Enable MMDC */
	69	+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
	70	+
	71	+ /* dram init sequence: update MRs */
	72	+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) \| CONFIGURATION_REQ \|
	73	+ CMD_LOAD_MODE_REG \| CMD_BANK_ADDR_2));
	74	+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ \| CMD_LOAD_MODE_REG \|
	75	+ CMD_BANK_ADDR_3));
	76	+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) \| CONFIGURATION_REQ \|
	77	+ CMD_LOAD_MODE_REG \| CMD_BANK_ADDR_1));
	78	+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) \|
	79	+ CMD_ADDR_LSB_MR_ADDR(0x30) \| CONFIGURATION_REQ \|
	80	+ CMD_LOAD_MODE_REG \| CMD_BANK_ADDR_0));
	81	+
	82	+ /* dram init sequence: ZQCL */
	83	+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) \| CONFIGURATION_REQ \|
	84	+ CMD_ZQ_CALIBRATION \| CMD_BANK_ADDR_0));
	85	+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
	86	+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
	87	+ FORCE_ZQ_AUTO_CALIBRATION);
	88	+
	89	+ /* Calibrations now: wr lvl */
	90	+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) \|
	91	+ CONFIGURATION_REQ \| CMD_LOAD_MODE_REG \|
	92	+ CMD_BANK_ADDR_1));
	93	+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ \| WL_EN \| CMD_NORMAL));
	94	+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
	95	+
	96	+ mdelay(1);
	97	+
	98	+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) \| CONFIGURATION_REQ \|
	99	+ CMD_LOAD_MODE_REG \| CMD_BANK_ADDR_1));
	100	+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
	101	+
	102	+ mdelay(1);
	103	+
	104	+ /* Calibrations now: Read DQS gating calibration */
	105	+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) \| CONFIGURATION_REQ \|
	106	+ CMD_PRECHARGE_BANK_OPEN \| CMD_BANK_ADDR_0));
	107	+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) \| CONFIGURATION_REQ \|
	108	+ CMD_LOAD_MODE_REG \| CMD_BANK_ADDR_3));
	109	+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
	110	+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
	111	+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
	112	+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
	113	+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
	114	+
	115	+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ \| CMD_LOAD_MODE_REG \|
	116	+ CMD_BANK_ADDR_3));
	117	+
	118	+ /* Calibrations now: Read calibration */
	119	+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) \| CONFIGURATION_REQ \|
	120	+ CMD_PRECHARGE_BANK_OPEN \| CMD_BANK_ADDR_0));
	121	+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) \| CONFIGURATION_REQ \|
	122	+ CMD_LOAD_MODE_REG \| CMD_BANK_ADDR_3));
	123	+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
	124	+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
	125	+ AUTO_RD_CALIBRATION_EN,
	126	+ AUTO_RD_CALIBRATION_EN);
	127	+
	128	+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ \| CMD_LOAD_MODE_REG \|
	129	+ CMD_BANK_ADDR_3));
	130	+
	131	+ /* PD, SR */
	132	+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
	133	+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
	134	+
	135	+ /* refresh scheme */
	136	+ set_wait_for_bits_clear(&mmdc->mdref,
	137	+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
	138	+ START_REFRESH);
	139	+
	140	+ /* disable CON_REQ */
	141	+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
	142	+}
	143	+
	144	+int dram_init(void)
	145	+{
	146	+ mmdc_init();
	147	+
	148	+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	149	+
	150	+ return 0;
	151	+}
	152	+
	153	+int board_eth_init(bd_t *bis)
	154	+{
	155	+ return pci_eth_init(bis);
	156	+}
	157	+
	158	+int board_early_init_f(void)
	159	+{
	160	+ fsl_lsch2_early_init_f();
	161	+
	162	+ return 0;
	163	+}
	164	+
	165	+int board_init(void)
	166	+{
	167	+ struct ccsr_cci400 cci = (struct ccsr_cci400 )CONFIG_SYS_CCI400_ADDR;
	168	+ /*
	169	+ * Set CCI-400 control override register to enable barrier
	170	+ * transaction
	171	+ */
	172	+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
	173	+
	174	+#ifdef CONFIG_ENV_IS_NOWHERE
	175	+ gd->env_addr = (ulong)&default_environment[0];
	176	+#endif
	177	+
	178	+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
	179	+ enable_layerscape_ns_access();
	180	+#endif
	181	+
	182	+ return 0;
	183	+}
	184	+
	185	+int ft_board_setup(void blob, bd_t bd)
	186	+{
	187	+ arch_fixup_fdt(blob);
	188	+
	189	+ ft_cpu_setup(blob, bd);
	190	+
	191	+ return 0;
	192	+}
	1	+CONFIG_ARM=y
	2	+CONFIG_TARGET_LS1012AFRDM=y
	3	+# CONFIG_SYS_MALLOC_F is not set
	4	+CONFIG_SPI_FLASH=y
	5	+CONFIG_DM_SPI=y
	6	+CONFIG_DM_SPI_FLASH=y
	7	+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
	8	+CONFIG_FIT=y
	9	+CONFIG_FIT_VERBOSE=y
	10	+CONFIG_OF_BOARD_SETUP=y
	11	+CONFIG_OF_STDOUT_VIA_ALIAS=y
	12	+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
	13	+CONFIG_HUSH_PARSER=y
	14	+CONFIG_CMD_GREPENV=y
	15	+CONFIG_CMD_SF=y
	16	+CONFIG_CMD_I2C=y
	17	+CONFIG_CMD_USB=y
	18	+# CONFIG_CMD_SETEXPR is not set
	19	+CONFIG_CMD_DHCP=y
	20	+CONFIG_CMD_MII=y
	21	+CONFIG_CMD_PING=y
	22	+CONFIG_CMD_CACHE=y
	23	+CONFIG_CMD_EXT2=y
	24	+CONFIG_CMD_FAT=y
	25	+CONFIG_OF_CONTROL=y
	26	+CONFIG_NET_RANDOM_ETHADDR=y
	27	+CONFIG_DM=y
	28	+CONFIG_NETDEVICES=y
	29	+CONFIG_SYS_NS16550=y