Commit ffc103732c82faa945c85bbb7c5c34c30b6fac72
Committed by
Tom Rini
1 parent
f91afc4d00
Exists in
v2017.01-smarct4x
and in
37 other branches
vexpress64: support the Juno Development Platform
The Juno Development Platform is a physical Versatile Express device with some differences from the emulated semihosting models. The main difference is that the system is split in a SoC and an FPGA where the SoC hosts the serial ports at totally different adresses. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Showing 5 changed files with 45 additions and 1 deletions Side-by-side Diff
arch/arm/Kconfig
board/armltd/vexpress64/Kconfig
board/armltd/vexpress64/MAINTAINERS
configs/vexpress_aemv8a_juno_defconfig
include/configs/vexpress_aemv8a.h
... | ... | @@ -21,7 +21,8 @@ |
21 | 21 | |
22 | 22 | #define CONFIG_REMAKE_ELF |
23 | 23 | |
24 | -#ifndef CONFIG_TARGET_VEXPRESS64_BASE_FVP | |
24 | +#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \ | |
25 | + !defined(CONFIG_TARGET_VEXPRESS64_JUNO) | |
25 | 26 | /* Base FVP and Juno not using GICv3 yet */ |
26 | 27 | #define CONFIG_GICV3 |
27 | 28 | #endif |
... | ... | @@ -44,6 +45,9 @@ |
44 | 45 | /* ATF loads u-boot here for BASE_FVP model */ |
45 | 46 | #define CONFIG_SYS_TEXT_BASE 0x88000000 |
46 | 47 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) |
48 | +#elif CONFIG_TARGET_VEXPRESS64_JUNO | |
49 | +#define CONFIG_SYS_TEXT_BASE 0xe0000000 | |
50 | +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) | |
47 | 51 | #else |
48 | 52 | #define CONFIG_SYS_TEXT_BASE 0x80000000 |
49 | 53 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) |
50 | 54 | |
... | ... | @@ -88,10 +92,15 @@ |
88 | 92 | #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) |
89 | 93 | #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) |
90 | 94 | |
95 | +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO | |
96 | +#define V2M_UART0 0x7ff80000 | |
97 | +#define V2M_UART1 0x7ff70000 | |
98 | +#else /* Not Juno */ | |
91 | 99 | #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) |
92 | 100 | #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) |
93 | 101 | #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) |
94 | 102 | #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) |
103 | +#endif | |
95 | 104 | |
96 | 105 | #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) |
97 | 106 | |
... | ... | @@ -122,6 +131,9 @@ |
122 | 131 | #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP |
123 | 132 | #define GICD_BASE (0x2f000000) |
124 | 133 | #define GICC_BASE (0x2c000000) |
134 | +#elif CONFIG_TARGET_VEXPRESS64_JUNO | |
135 | +#define GICD_BASE (0x2C010000) | |
136 | +#define GICC_BASE (0x2C02f000) | |
125 | 137 | #else |
126 | 138 | #define GICD_BASE (0x2C001000) |
127 | 139 | #define GICC_BASE (0x2C002000) |
128 | 140 | |
... | ... | @@ -140,7 +152,11 @@ |
140 | 152 | |
141 | 153 | /* PL011 Serial Configuration */ |
142 | 154 | #define CONFIG_PL011_SERIAL |
155 | +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO | |
156 | +#define CONFIG_PL011_CLOCK 7273800 | |
157 | +#else | |
143 | 158 | #define CONFIG_PL011_CLOCK 24000000 |
159 | +#endif | |
144 | 160 | #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ |
145 | 161 | (void *)CONFIG_SYS_SERIAL1} |
146 | 162 | #define CONFIG_CONS_INDEX 0 |
... | ... | @@ -161,6 +177,7 @@ |
161 | 177 | #define CONFIG_CMD_ENV |
162 | 178 | #define CONFIG_CMD_FLASH |
163 | 179 | #define CONFIG_CMD_IMI |
180 | +#define CONFIG_CMD_LOADB | |
164 | 181 | #define CONFIG_CMD_MEMORY |
165 | 182 | #define CONFIG_CMD_MII |
166 | 183 | #define CONFIG_CMD_NET |