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Commit ffc7bc56e76f9293e2f613bc82ed2e5d08ecb189

Authored by Adrian Alonso
1 parent e644db2827
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividers 

Adjust ahb/axi clock root podf dividers to be divided by 1
to allow ahb/axi clock root to be 24Mhz when sourced
from osc_clk.

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(Cherry picked from commit 9e80234c823d6a2a0d9e10ab4c4c605bf646bd22)

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

board/freescale/mx6qarm2/mt128x64mx32.cfg
Diff comments   View file @ ffc7bc5
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 * 5 *
6 * Refer doc/README.imximage for more details about how-to configure 6 * Refer doc/README.imximage for more details about how-to configure
7 * and create imximage boot image 7 * and create imximage boot image
8 * 8 *
9 * The syntax is taken as close as possible with the kwbimage 9 * The syntax is taken as close as possible with the kwbimage
10 */ 10 */
11 11
12 #define __ASSEMBLY__ 12 #define __ASSEMBLY__
13 #include <config.h> 13 #include <config.h>
14 14
15 /* image version */ 15 /* image version */
16 IMAGE_VERSION 2 16 IMAGE_VERSION 2
17 17
18 /* 18 /*
19 * Boot Device : one of 19 * Boot Device : one of
20 * spi, sd (the board has no nand neither onenand) 20 * spi, sd (the board has no nand neither onenand)
21 */ 21 */
22 BOOT_FROM sd 22 BOOT_FROM sd
23 23
24 #ifdef CONFIG_USE_PLUGIN 24 #ifdef CONFIG_USE_PLUGIN
25 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ 25 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
26 PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 26 PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000
27 #else 27 #else
28 28
29 #ifdef CONFIG_SECURE_BOOT 29 #ifdef CONFIG_SECURE_BOOT
30 CSF CONFIG_CSF_SIZE 30 CSF CONFIG_CSF_SIZE
31 #endif 31 #endif
32 32
33 /* 33 /*
34 * Device Configuration Data (DCD) 34 * Device Configuration Data (DCD)
35 * 35 *
36 * Each entry must have the format: 36 * Each entry must have the format:
37 * Addr-type Address Value 37 * Addr-type Address Value
38 * 38 *
39 * where: 39 * where:
40 * Addr-type register length (1,2 or 4 bytes) 40 * Addr-type register length (1,2 or 4 bytes)
41 * Address absolute address of the register 41 * Address absolute address of the register
42 * value value to be stored in the register 42 * value value to be stored in the register
43 */ 43 */
44 #ifdef CONFIG_MX6DQ_POP_LPDDR2 44 #ifdef CONFIG_MX6DQ_POP_LPDDR2
45 /* set ddr to 400Mhz */ 45 /* set ddr to 400Mhz */
46 DATA 4 0x020C4018 0x21324 46 DATA 4 0x020C4018 0x21324
47 DATA 4 0x020C4014 0x2018900 47 DATA 4 0x020C4014 0x2018100
48 CHECK_BITS_CLR 4 0x020C4048 0x3F 48 CHECK_BITS_CLR 4 0x020C4048 0x3F
49 DATA 4 0x020C4018 0x61324 49 DATA 4 0x020C4018 0x61324
50 DATA 4 0x020C4014 0x18900 50 DATA 4 0x020C4014 0x18900
51 CHECK_BITS_CLR 4 0x020C4048 0x3F 51 CHECK_BITS_CLR 4 0x020C4048 0x3F
52 DATA 4 0x020C4018 0x60324 52 DATA 4 0x020C4018 0x60324
53 53
54 DATA 4 0x020c4068 0xffffffff 54 DATA 4 0x020c4068 0xffffffff
55 DATA 4 0x020c406c 0xffffffff 55 DATA 4 0x020c406c 0xffffffff
56 DATA 4 0x020c4070 0xffffffff 56 DATA 4 0x020c4070 0xffffffff
57 DATA 4 0x020c4074 0xffffffff 57 DATA 4 0x020c4074 0xffffffff
58 DATA 4 0x020c4078 0xffffffff 58 DATA 4 0x020c4078 0xffffffff
59 DATA 4 0x020c407c 0xffffffff 59 DATA 4 0x020c407c 0xffffffff
60 DATA 4 0x020c4080 0xffffffff 60 DATA 4 0x020c4080 0xffffffff
61 DATA 4 0x020c4084 0xffffffff 61 DATA 4 0x020c4084 0xffffffff
62 // Switch PL301_FAST2 to DDR dual channel mapping 62 // Switch PL301_FAST2 to DDR dual channel mapping
63 //DATA 4 0x00B00000 0x1 63 //DATA 4 0x00B00000 0x1
64 64
65 //============================================================================= 65 //=============================================================================
66 /// IOMUX 66 /// IOMUX
67 //============================================================================= 67 //=============================================================================
68 //DDR IO TYPE: 68 //DDR IO TYPE:
69 DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE 69 DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
70 DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE 70 DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
71 71
72 //CLOCK: 72 //CLOCK:
73 DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 73 DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
74 DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 74 DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
75 75
76 //Control: 76 //Control:
77 DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 77 DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
78 DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 78 DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
79 DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 79 DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
80 DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS 80 DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
81 DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 81 DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
82 DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 82 DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
83 DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS 83 DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
84 DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS 84 DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
85 85
86 //Data Strobes: 86 //Data Strobes:
87 DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 87 DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
88 DATA 4 0x020e05a8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 88 DATA 4 0x020e05a8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
89 DATA 4 0x020e05b0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 89 DATA 4 0x020e05b0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
90 DATA 4 0x020e0524 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 90 DATA 4 0x020e0524 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
91 DATA 4 0x020e051c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 91 DATA 4 0x020e051c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
92 DATA 4 0x020e0518 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 92 DATA 4 0x020e0518 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
93 DATA 4 0x020e050c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 93 DATA 4 0x020e050c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
94 DATA 4 0x020e05b8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 94 DATA 4 0x020e05b8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
95 DATA 4 0x020e05c0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 95 DATA 4 0x020e05c0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
96 96
97 //Data: 97 //Data:
98 DATA 4 0x020e0798 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 98 DATA 4 0x020e0798 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
99 DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS 99 DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS
100 DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS 100 DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS
101 DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS 101 DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS
102 DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS 102 DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS
103 DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS 103 DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS
104 DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS 104 DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS
105 DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS 105 DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS
106 DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS 106 DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS
107 107
108 DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 108 DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
109 DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 109 DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
110 DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 110 DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
111 DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 111 DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
112 DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 112 DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
113 DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 113 DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
114 DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 114 DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
115 DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 115 DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
116 116
117 //============================================================================= 117 //=============================================================================
118 // DDR Controller Registers 118 // DDR Controller Registers
119 //============================================================================= 119 //=============================================================================
120 // Manufacturer: Micron - POP Package 120 // Manufacturer: Micron - POP Package
121 // Device Part Number: MT42L128M64D2LL-25WT 121 // Device Part Number: MT42L128M64D2LL-25WT
122 // Clock Freq.: 400MHz 122 // Clock Freq.: 400MHz
123 // Density per CS in Gb: 4 123 // Density per CS in Gb: 4
124 // Chip Selects used: 1 124 // Chip Selects used: 1
125 // Number of channels 2 125 // Number of channels 2
126 // Density per channel (Gb) 4 126 // Density per channel (Gb) 4
127 // Total DRAM density (Gb) 8 127 // Total DRAM density (Gb) 8
128 // Number of Banks: 8 128 // Number of Banks: 8
129 // Row address: 14 129 // Row address: 14
130 // Column address: 10 130 // Column address: 10
131 // Data bus width 32 131 // Data bus width 32
132 //============================================================================= 132 //=============================================================================
133 133
134 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up 134 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
135 DATA 4 0x021b001c 0x00008000 // Chan 0 135 DATA 4 0x021b001c 0x00008000 // Chan 0
136 DATA 4 0x021b401c 0x00008000 // Chan 1 136 DATA 4 0x021b401c 0x00008000 // Chan 1
137 137
138 DATA 4 0x021b085c 0x1b5f0109 //LPDDR2 ZQ params 138 DATA 4 0x021b085c 0x1b5f0109 //LPDDR2 ZQ params
139 DATA 4 0x021b485c 0x1b5f0109 //LPDDR2 ZQ params 139 DATA 4 0x021b485c 0x1b5f0109 //LPDDR2 ZQ params
140 140
141 //============================================================================= 141 //=============================================================================
142 // Calibration setup. 142 // Calibration setup.
143 // 143 //
144 //============================================================================= 144 //=============================================================================
145 DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable one time ZQ calibration 145 DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable one time ZQ calibration
146 DATA 4 0x021b4800 0xa1380003 // DDR_PHY_P1_MPZQHWCTRL 146 DATA 4 0x021b4800 0xa1380003 // DDR_PHY_P1_MPZQHWCTRL
147 147
148 DATA 4 0x021b0890 0x00400000 //ca bus abs delay 148 DATA 4 0x021b0890 0x00400000 //ca bus abs delay
149 DATA 4 0x021b4890 0x00400000 //ca bus abs delay 149 DATA 4 0x021b4890 0x00400000 //ca bus abs delay
150 150
151 //DATA 4 0x021b48bc0x00055555 // DDR_PHY_P1_MPWRCADL 151 //DATA 4 0x021b48bc0x00055555 // DDR_PHY_P1_MPWRCADL
152 152
153 DATA 4 0x021b08b8 0x00000800 //frc_msr. 153 DATA 4 0x021b08b8 0x00000800 //frc_msr.
154 DATA 4 0x021b48b8 0x00000800 //frc_msr. 154 DATA 4 0x021b48b8 0x00000800 //frc_msr.
155 155
156 // read delays, settings recommended by design to remain constant 156 // read delays, settings recommended by design to remain constant
157 DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3 157 DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
158 DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3 158 DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
159 DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3 159 DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
160 DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3 160 DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
161 DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3 161 DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
162 DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3 162 DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
163 DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3 163 DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
164 DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3 164 DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
165 165
166 // write delays, settings recommended by design to remain constant 166 // write delays, settings recommended by design to remain constant
167 DATA 4 0x021b082c 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 167 DATA 4 0x021b082c 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
168 DATA 4 0x021b0830 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 168 DATA 4 0x021b0830 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
169 DATA 4 0x021b0834 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 169 DATA 4 0x021b0834 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
170 DATA 4 0x021b0838 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 170 DATA 4 0x021b0838 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3
171 DATA 4 0x021b482c 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 171 DATA 4 0x021b482c 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
172 DATA 4 0x021b4830 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 172 DATA 4 0x021b4830 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
173 DATA 4 0x021b4834 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 173 DATA 4 0x021b4834 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
174 DATA 4 0x021b4838 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 174 DATA 4 0x021b4838 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3
175 175
176 DATA 4 0x021b0848 0x36383644 // MPRDDLCTL PHY0 176 DATA 4 0x021b0848 0x36383644 // MPRDDLCTL PHY0
177 DATA 4 0x021b4848 0x3a383846 // MPRDDLCTL PHY1 177 DATA 4 0x021b4848 0x3a383846 // MPRDDLCTL PHY1
178 178
179 DATA 4 0x021b0850 0x38343E34 // MPWRDLCTL PHY0 179 DATA 4 0x021b0850 0x38343E34 // MPWRDLCTL PHY0
180 DATA 4 0x021b4850 0x48384A44 // MPWRDLCTL PHY1 180 DATA 4 0x021b4850 0x48384A44 // MPWRDLCTL PHY1
181 181
182 DATA 4 0x021b083c 0x20000000 //PHY0 dqs gating dis 182 DATA 4 0x021b083c 0x20000000 //PHY0 dqs gating dis
183 DATA 4 0x021b0840 0x0 183 DATA 4 0x021b0840 0x0
184 DATA 4 0x021b483c 0x20000000 //PHY0 dqs gating dis 184 DATA 4 0x021b483c 0x20000000 //PHY0 dqs gating dis
185 DATA 4 0x021b4840 0x0 185 DATA 4 0x021b4840 0x0
186 186
187 //For i.mx6qd parts of versions C and later (v1.2, v1.3). 187 //For i.mx6qd parts of versions C and later (v1.2, v1.3).
188 DATA 4 0x021b08c0 0x24921492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 188 DATA 4 0x021b08c0 0x24921492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
189 DATA 4 0x021b48c0 0x24921492 189 DATA 4 0x021b48c0 0x24921492
190 190
191 DATA 4 0x021b08b8 0x00000800 //frc_msr. 191 DATA 4 0x021b08b8 0x00000800 //frc_msr.
192 DATA 4 0x021b48b8 0x00000800 //frc_msr. 192 DATA 4 0x021b48b8 0x00000800 //frc_msr.
193 //============================================================================= 193 //=============================================================================
194 // Calibration setup end 194 // Calibration setup end
195 //============================================================================= 195 //=============================================================================
196 196
197 // Channel0 - starting address 0x80000000 197 // Channel0 - starting address 0x80000000
198 DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0 198 DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0
199 DATA 4 0x021b0004 0x00020024 // MMDC0_MDPDC 199 DATA 4 0x021b0004 0x00020024 // MMDC0_MDPDC
200 DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1 200 DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1
201 DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2 201 DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2
202 202
203 //MDMISC: RALAT kept to the high level of 5. 203 //MDMISC: RALAT kept to the high level of 5.
204 //MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 204 //MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
205 //a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 205 //a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
206 //b. Small performence improvment 206 //b. Small performence improvment
207 DATA 4 0x021b0018 0x0000174C // MMDC0_MDMISC 207 DATA 4 0x021b0018 0x0000174C // MMDC0_MDMISC
208 DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD 208 DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD
209 DATA 4 0x021b0030 0x009F0E10 // MMDC0_MDOR 209 DATA 4 0x021b0030 0x009F0E10 // MMDC0_MDOR
210 DATA 4 0x021b0038 0x001A0889 // MMDC0_MDCFG3LP 210 DATA 4 0x021b0038 0x001A0889 // MMDC0_MDCFG3LP
211 DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC 211 DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC
212 DATA 4 0x021b0040 0x0000004F // Chan0 CS0_END 2 channel with 2 Channel fixed mode 212 DATA 4 0x021b0040 0x0000004F // Chan0 CS0_END 2 channel with 2 Channel fixed mode
213 // DATA 4 0x021b0400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled 213 // DATA 4 0x021b0400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
214 DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL 214 DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL
215 215
216 // Channel1 - starting address 0x10000000 216 // Channel1 - starting address 0x10000000
217 // Note: the values for Chan1 should match those of Chan0 217 // Note: the values for Chan1 should match those of Chan0
218 DATA 4 0x021b400c 0x33374133 // MMDC1_MDCFG0 218 DATA 4 0x021b400c 0x33374133 // MMDC1_MDCFG0
219 DATA 4 0x021b4004 0x00020024 // MMDC1_MDPDC 219 DATA 4 0x021b4004 0x00020024 // MMDC1_MDPDC
220 DATA 4 0x021b4010 0x00100A82 // MMDC1_MDCFG1 220 DATA 4 0x021b4010 0x00100A82 // MMDC1_MDCFG1
221 DATA 4 0x021b4014 0x00000093 // MMDC1_MDCFG2 221 DATA 4 0x021b4014 0x00000093 // MMDC1_MDCFG2
222 DATA 4 0x021b4018 0x0000174C // MMDC1_MDMISC 222 DATA 4 0x021b4018 0x0000174C // MMDC1_MDMISC
223 DATA 4 0x021b402c 0x0F9F26D2 // MMDC1_MDRWD 223 DATA 4 0x021b402c 0x0F9F26D2 // MMDC1_MDRWD
224 DATA 4 0x021b4030 0x009F0E10 // MMDC1_MDOR 224 DATA 4 0x021b4030 0x009F0E10 // MMDC1_MDOR
225 DATA 4 0x021b4038 0x001A0889 // MMDC1_MDCFG3LP 225 DATA 4 0x021b4038 0x001A0889 // MMDC1_MDCFG3LP
226 DATA 4 0x021b4008 0x00000000 // MMDC1_MDOTC 226 DATA 4 0x021b4008 0x00000000 // MMDC1_MDOTC
227 DATA 4 0x021b4040 0x00000017 // Chan1 CS0_END 227 DATA 4 0x021b4040 0x00000017 // Chan1 CS0_END
228 // DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled 228 // DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
229 DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL 229 DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL
230 230
231 //============================================================================= 231 //=============================================================================
232 // LPDDR2 Mode Register Writes 232 // LPDDR2 Mode Register Writes
233 //============================================================================= 233 //=============================================================================
234 // Channel 0 CS0 234 // Channel 0 CS0
235 DATA 4 0x021b001c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset) 235 DATA 4 0x021b001c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset)
236 DATA 4 0x021b001c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) 236 DATA 4 0x021b001c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
237 DATA 4 0x021b001c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration 237 DATA 4 0x021b001c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration
238 DATA 4 0x021b001c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration 238 DATA 4 0x021b001c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration
239 DATA 4 0x021b001c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration 239 DATA 4 0x021b001c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration
240 // Channel 0 CS1 240 // Channel 0 CS1
241 // Note, CS1 does not exist in this memory hence these writes are commented out 241 // Note, CS1 does not exist in this memory hence these writes are commented out
242 // They are only shown here for completeness 242 // They are only shown here for completeness
243 // If you use a memory where CS1 exists, simply uncomment these lines 243 // If you use a memory where CS1 exists, simply uncomment these lines
244 //DATA 4 0x021b001c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset) 244 //DATA 4 0x021b001c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset)
245 //DATA 4 0x021b001c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) 245 //DATA 4 0x021b001c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
246 //DATA 4 0x021b001c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration 246 //DATA 4 0x021b001c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration
247 //DATA 4 0x021b001c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration 247 //DATA 4 0x021b001c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration
248 //DATA 4 0x021b001c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration 248 //DATA 4 0x021b001c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration
249 249
250 // For Channel 1 mode register writes - these should match channel 0 settings 250 // For Channel 1 mode register writes - these should match channel 0 settings
251 // Channel 1 CS0 251 // Channel 1 CS0
252 DATA 4 0x021b401c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset) 252 DATA 4 0x021b401c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset)
253 DATA 4 0x021b401c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) 253 DATA 4 0x021b401c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
254 DATA 4 0x021b401c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration 254 DATA 4 0x021b401c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration
255 DATA 4 0x021b401c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration 255 DATA 4 0x021b401c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration
256 DATA 4 0x021b401c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration 256 DATA 4 0x021b401c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration
257 // Channel 1 CS1 257 // Channel 1 CS1
258 // Note, CS1 does not exist in this memory hence these writes are commented out 258 // Note, CS1 does not exist in this memory hence these writes are commented out
259 // They are only shown here for completeness 259 // They are only shown here for completeness
260 // If you use a memory where CS1 exists, simply uncomment these lines 260 // If you use a memory where CS1 exists, simply uncomment these lines
261 //DATA 4 0x021b401c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset) 261 //DATA 4 0x021b401c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset)
262 //DATA 4 0x021b401c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) 262 //DATA 4 0x021b401c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)
263 //DATA 4 0x021b401c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration 263 //DATA 4 0x021b401c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration
264 //DATA 4 0x021b401c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration 264 //DATA 4 0x021b401c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration
265 //DATA 4 0x021b401c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration 265 //DATA 4 0x021b401c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration
266 266
267 //////////#################################################// 267 //////////#################################################//
268 //final DDR setup, before operation start: 268 //final DDR setup, before operation start:
269 269
270 DATA 4 0x021b0020 0x00001800 // MMDC0_MDREF 270 DATA 4 0x021b0020 0x00001800 // MMDC0_MDREF
271 DATA 4 0x021b4020 0x00001800 // MMDC1_MDREF, align with Chan 0 setting 271 DATA 4 0x021b4020 0x00001800 // MMDC1_MDREF, align with Chan 0 setting
272 272
273 DATA 4 0x021b0818 0x0 // DDR_PHY_P0_MPODTCTRL 273 DATA 4 0x021b0818 0x0 // DDR_PHY_P0_MPODTCTRL
274 DATA 4 0x021b4818 0x0 // DDR_PHY_P1_MPODTCTRL 274 DATA 4 0x021b4818 0x0 // DDR_PHY_P1_MPODTCTRL
275 275
276 DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr 276 DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
277 DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P1_MPMUR0, frc_msr 277 DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P1_MPMUR0, frc_msr
278 278
279 DATA 4 0x021b0004 0x00025564 // MMDC0_MDPDC now SDCTL power down enabled 279 DATA 4 0x021b0004 0x00025564 // MMDC0_MDPDC now SDCTL power down enabled
280 DATA 4 0x021b4004 0x00025564 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting 280 DATA 4 0x021b4004 0x00025564 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting
281 281
282 DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled 282 DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled
283 DATA 4 0x021b4404 0x00011006 //MMDC1_MAPSR ADOPT power down enabled, align with Chan 0 setting 283 DATA 4 0x021b4404 0x00011006 //MMDC1_MAPSR ADOPT power down enabled, align with Chan 0 setting
284 284
285 DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register 285 DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register
286 DATA 4 0x021b401c 0x00000000 // MMDC1_MDSCR, clear this register 286 DATA 4 0x021b401c 0x00000000 // MMDC1_MDSCR, clear this register
287 287
288 /* enable AXI cache for VDOA/VPU/IPU */ 288 /* enable AXI cache for VDOA/VPU/IPU */
289 DATA 4, 0x020e0010, 0xF00000CF 289 DATA 4, 0x020e0010, 0xF00000CF
290 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 290 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
291 DATA 4, 0x020e0018, 0x007F007F 291 DATA 4, 0x020e0018, 0x007F007F
292 DATA 4, 0x020e001c, 0x007F007F 292 DATA 4, 0x020e001c, 0x007F007F
293 #endif 293 #endif
294 #endif 294 #endif
295 295