Commit ffc7bc56e76f9293e2f613bc82ed2e5d08ecb189

Authored by Adrian Alonso
1 parent e644db2827

MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividers

Adjust ahb/axi clock root podf dividers to be divided by 1
to allow ahb/axi clock root to be 24Mhz when sourced
from osc_clk.

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(Cherry picked from commit 9e80234c823d6a2a0d9e10ab4c4c605bf646bd22)

Showing 1 changed file with 1 additions and 1 deletions Side-by-side Diff

board/freescale/mx6qarm2/mt128x64mx32.cfg
... ... @@ -44,7 +44,7 @@
44 44 #ifdef CONFIG_MX6DQ_POP_LPDDR2
45 45 /* set ddr to 400Mhz */
46 46 DATA 4 0x020C4018 0x21324
47   -DATA 4 0x020C4014 0x2018900
  47 +DATA 4 0x020C4014 0x2018100
48 48 CHECK_BITS_CLR 4 0x020C4048 0x3F
49 49 DATA 4 0x020C4018 0x61324
50 50 DATA 4 0x020C4014 0x18900