omap4: duovero: Add Gumstix DuoVero machine.

This adds the Gumstix DuoVero machine [1]. This is a OMAP4430-based computer-on-module (COM aka SOM) that can be mounted on various expansion boards with different peripherals. [1] https://store.gumstix.com/index.php/category/43/ Signed-off-by: Ash Charles <ash@gumstix.com> [trini: Rename gpmc_enable_gpmc_cs_config to gpmc_enable_gpmc_net_config] Signed-off-by: Tom Rini <trini@ti.com>

omap4: duovero: Add Gumstix DuoVero machine.
This adds the Gumstix DuoVero machine [1]. This is a OMAP4430-based computer-on-module (COM aka SOM) that can be mounted on various expansion boards with different peripherals. [1] https://store.gumstix.com/index.php/category/43/ Signed-off-by: Ash Charles <ash@gumstix.com> [trini: Rename gpmc_enable_gpmc_cs_config to gpmc_enable_gpmc_net_config] Signed-off-by: Tom Rini <trini@ti.com>
Ash Charles · Tom Rini
1 parent 939911a64b
Showing 6 changed files with 543 additions and 0 deletions Side-by-side Diff
board/gumstix/duovero/Makefile
board/gumstix/duovero/duovero.c
board/gumstix/duovero/duovero_mux_data.h
boards.cfg
include/configs/duovero.h
include/configs/ti_omap4_common.h
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= duovero.o
+/*
+ * (C) Copyright 2013
+ * Gumstix Inc. <www.gumstix.com>
+ * Maintainer: Ash Charles  <ash@gumstix.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <twl6030.h>
+#include <asm/emif.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+
+#include "duovero_mux_data.h"
+
+#define WIFI_EN	43
+
+#if defined(CONFIG_CMD_NET)
+#define SMSC_NRESET	45
+static void setup_net_chip(void);
+#endif
+
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: duovero\n"
+};
+
+struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+	int ret = 0;
+	u8 val;
+
+	/* wifi setup: first enable 32Khz clock from 6030 pmic */
+	val = 0xe1;
+	ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
+	if (ret)
+		printf("Failed to enable 32Khz clock to wifi module\n");
+
+	/* then setup WIFI_EN as an output pin and send reset pulse */
+	if (!gpio_request(WIFI_EN, "")) {
+		gpio_direction_output(WIFI_EN, 0);
+		gpio_set_value(WIFI_EN, 1);
+		udelay(1);
+		gpio_set_value(WIFI_EN, 0);
+		udelay(1);
+		gpio_set_value(WIFI_EN, 1);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+	return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux((*ctrl)->control_padconf_core_base,
+		   core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux((*ctrl)->control_padconf_wkup_base,
+		   wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+
+#if defined(CONFIG_CMD_NET)
+
+#define GPMC_SIZE_16M	0xF
+#define GPMC_BASEADDR_MASK	0x3F
+#define GPMC_CS_ENABLE		0x1
+
+static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs,
+		u32 base, u32 size)
+{
+	writel(0, &cs->config7);
+	sdelay(1000);
+	/* Delay for settling */
+	writel(gpmc_config[0], &cs->config1);
+	writel(gpmc_config[1], &cs->config2);
+	writel(gpmc_config[2], &cs->config3);
+	writel(gpmc_config[3], &cs->config4);
+	writel(gpmc_config[4], &cs->config5);
+	writel(gpmc_config[5], &cs->config6);
+
+	/*
+	 * Enable the config.  size is the CS size and goes in
+	 * bits 11:8.  We set bit 6 to enable this CS and the base
+	 * address goes into bits 5:0.
+	 */
+	writel((size << 8) | (GPMC_CS_ENABLE << 6) |
+				 ((base >> 24) & GPMC_BASEADDR_MASK),
+				 &cs->config7);
+
+	sdelay(2000);
+}
+
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x2a001203
+#define NET_LAN9221_GPMC_CONFIG2    0x000a0a02
+#define NET_LAN9221_GPMC_CONFIG3    0x00020200
+#define NET_LAN9221_GPMC_CONFIG4    0x0a030a03
+#define NET_LAN9221_GPMC_CONFIG5    0x000a0a0a
+#define NET_LAN9221_GPMC_CONFIG6    0x8a070707
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
+/* GPMC definitions for LAN9221 chips on expansion boards */
+static const u32 gpmc_lan_config[] = {
+	NET_LAN9221_GPMC_CONFIG1,
+	NET_LAN9221_GPMC_CONFIG2,
+	NET_LAN9221_GPMC_CONFIG3,
+	NET_LAN9221_GPMC_CONFIG4,
+	NET_LAN9221_GPMC_CONFIG5,
+	NET_LAN9221_GPMC_CONFIG6,
+	/*CONFIG7- computed as params */
+};
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *	      Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+			      GPMC_SIZE_16M);
+
+	/* Make GPIO SMSC_NRESET as output pin and send reset pulse */
+	if (!gpio_request(SMSC_NRESET, "")) {
+		gpio_direction_output(SMSC_NRESET, 0);
+		gpio_set_value(SMSC_NRESET, 1);
+		udelay(1);
+		gpio_set_value(SMSC_NRESET, 0);
+		udelay(1);
+		gpio_set_value(SMSC_NRESET, 1);
+	}
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_USB_EHCI
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	int ret;
+	unsigned int utmi_clk;
+	u32 auxclk, altclksrc;
+
+	/* Now we can enable our port clocks */
+	utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
+	utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
+	setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
+
+	auxclk = readl(&scrm->auxclk3);
+	/* Select sys_clk */
+	auxclk &= ~AUXCLK_SRCSELECT_MASK;
+	auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
+	/* Set the divisor to 2 */
+	auxclk &= ~AUXCLK_CLKDIV_MASK;
+	auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
+	/* Request auxilary clock #3 */
+	auxclk |= AUXCLK_ENABLE_MASK;
+	writel(auxclk, &scrm->auxclk3);
+
+	altclksrc = readl(&scrm->altclksrc);
+
+	/* Activate alternate system clock supplier */
+	altclksrc &= ~ALTCLKSRC_MODE_MASK;
+	altclksrc |= ALTCLKSRC_MODE_ACTIVE;
+
+	/* enable clocks */
+	altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
+
+	writel(altclksrc, &scrm->altclksrc);
+
+	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+	return omap_ehci_hcd_stop();
+}
+#endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+	return 0x20;
+}
+/*
+ * (C) Copyright 2012
+ * Gumstix Incorporated, <www.gumstix.com>
+ * Maintainer: Ash Charles <ash@gumstix.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _DUOVERO_MUX_DATA_H_
+#define _DUOVERO_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+	{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+	{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+	{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+	{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+	{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+	{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+	{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+	{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+	{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+	{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+	{UART3_RX_IRRX, (PTU | IEN | M0)},			/* uart3_rx */
+	{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+	{PAD1_SR_SCL, (PTU | IEN | M0)},			/* sr_scl */
+	{PAD0_SR_SDA, (PTU | IEN | M0)},			/* sr_sda */
+	{PAD1_SYS_32K, (IEN | M0)}				/* sys_32k */
+};
+
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
+	{GPMC_AD0, (PTU | IEN | M0)},				/* gpmc_ad0 */
+	{GPMC_AD1, (PTU | IEN | M0)},				/* gpmc_ad1 */
+	{GPMC_AD2, (PTU | IEN | M0)},				/* gpmc_ad2 */
+	{GPMC_AD3, (PTU | IEN | M0)},				/* gpmc_ad3 */
+	{GPMC_AD4, (PTU | IEN | M0)},				/* gpmc_ad4 */
+	{GPMC_AD5, (PTU | IEN | M0)},				/* gpmc_ad5 */
+	{GPMC_AD6, (PTU | IEN | M0)},				/* gpmc_ad6 */
+	{GPMC_AD7, (PTU | IEN | M0)},				/* gpmc_ad7 */
+	{GPMC_AD8, (PTU | IEN | M0)},				/* gpmc_ad8 */
+	{GPMC_AD9, (PTU | IEN | M0)},				/* gpmc_ad9 */
+	{GPMC_AD10, (PTU | IEN | M0)},				/* gpmc_ad10 */
+	{GPMC_AD11, (PTU | IEN | M0)},				/* gpmc_ad11 */
+	{GPMC_AD12, (PTU | IEN | M0)},				/* gpmc_ad12 */
+	{GPMC_AD13, (PTU | IEN | M0)},				/* gpmc_ad13 */
+	{GPMC_AD14, (PTU | IEN | M0)},				/* gpmc_ad14 */
+	{GPMC_AD15, (PTU | IEN | M0)},				/* gpmc_ad15 */
+	{GPMC_A16, (PTU | IEN | M3)},				/* gpio_40 */
+	{GPMC_A17, (PTU | IEN | M3)},				/* gpio_41 - hdmi_ls_oe */
+	{GPMC_A18, (PTU | IEN | M3)},				/* gpio_42 */
+	{GPMC_A19, (PTU | IEN | M3)},				/* gpio_43 - wifi_en */
+	{GPMC_A20, (PTU | IEN | M3)},				/* gpio_44 - eth_irq */
+	{GPMC_A21, (PTU | IEN | M3)},				/* gpio_45 - eth_nreset */
+	{GPMC_A22, (PTU | IEN | M3)},				/* gpio_46 - eth_pme */
+	{GPMC_A23, (PTU | IEN | M3)},				/* gpio_47 */
+	{GPMC_A24, (PTU | IEN | M3)},				/* gpio_48 - eth_mdix */
+	{GPMC_A25, (PTU | IEN | M3)},				/* gpio_49 - bt_wakeup */
+	{GPMC_NCS0, (PTU | M0)},				/* gpmc_ncs0 */
+	{GPMC_NCS1, (PTU | M0)},				/* gpmc_ncs1 */
+	{GPMC_NCS2, (PTU | M0)},				/* gpmc_ncs2 */
+	{GPMC_NCS3, (PTU | IEN | M3)},				/* gpio_53  */
+	{C2C_DATA12, (PTU | M0)},				/* gpmc_ncs4 */
+	{C2C_DATA13, (PTU | M0)},				/* gpmc_ncs5 - eth_cs */
+	{GPMC_NWP, (PTU | IEN | M0)},				/* gpmc_nwp */
+	{GPMC_CLK, (PTU | IEN | M0)},				/* gpmc_clk */
+	{GPMC_NADV_ALE, (PTU | M0)},				/* gpmc_nadv_ale */
+	{GPMC_NBE0_CLE, (PTU | M0)},				/* gpmc_nbe0_cle */
+	{GPMC_NBE1, (PTU | M0)},				/* gpmc_nbe1 */
+	{GPMC_WAIT0, (PTU | IEN | M0)},				/* gpmc_wait0 */
+	{GPMC_WAIT1,  (PTU | IEN | M0)},			/* gpio_62 - usbh_nreset */
+	{GPMC_NOE, (PTU | M0)},					/* gpmc_noe */
+	{GPMC_NWE, (PTU | M0)},					/* gpmc_nwe */
+	{HDMI_HPD, (PTD | IEN | M3)},				/* gpio_63 - hdmi_hpd */
+	{HDMI_CEC, (PTU | IEN | M0)},				/* hdmi_cec */
+	{HDMI_DDC_SCL, (M0)},					/* hdmi_ddc_scl */
+	{HDMI_DDC_SDA, (IEN | M0)},				/* hdmi_ddc_sda */
+	{CSI21_DX0, (IEN | M0)},				/* csi21_dx0 */
+	{CSI21_DY0, (IEN | M0)},				/* csi21_dy0 */
+	{CSI21_DX1, (IEN | M0)},				/* csi21_dx1 */
+	{CSI21_DY1, (IEN | M0)},				/* csi21_dy1 */
+	{CSI21_DX2, (IEN | M0)},				/* csi21_dx2 */
+	{CSI21_DY2, (IEN | M0)},				/* csi21_dy2 */
+	{CSI21_DX3, (IEN | M0)},				/* csi21_dx3 */
+	{CSI21_DY3, (IEN | M0)},				/* csi21_dy3 */
+	{CSI21_DX4, (IEN | M0)},				/* csi21_dx4 */
+	{CSI21_DY4, (IEN | M0)},				/* csi21_dy4 */
+	{CSI22_DX0, (IEN | M0)},				/* csi22_dx0 */
+	{CSI22_DY0, (IEN | M0)},				/* csi22_dy0 */
+	{CSI22_DX1, (IEN | M0)},				/* csi22_dx1 */
+	{CSI22_DY1, (IEN | M0)},				/* csi22_dy1 */
+	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
+	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
+	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
+	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
+	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+	{USBB1_HSIC_DATA, (PTU | IEN | M3)},				/* gpio_96 - usbh_cpen */
+	{USBB1_HSIC_STROBE, (PTU | IEN | M3)},				/* gpio_97 - usbh_reset */
+	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
+	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
+	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
+	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
+	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
+	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
+	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
+	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
+	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
+	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
+	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
+	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
+	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
+	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
+	{UART2_RTS, (M0)},						/* uart2_rts */
+	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
+	{UART2_TX, (M0)},						/* uart2_tx */
+	{HDQ_SIO, (M0)},						/* hdq-sio */
+	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
+	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
+	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
+	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
+	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs1 */
+	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_clk */
+	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
+	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
+	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
+	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
+	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
+	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
+	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
+	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
+	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
+	{UART4_RX, (IEN | PTU | M0)},					/* uart4_rx */
+	{UART4_TX, (M0)},						/* uart4_tx */
+	{USBB2_ULPITLL_CLK, (PTU | IEN | M3)},				/* gpio_157 - start_adc */
+	{USBB2_ULPITLL_STP, (PTU | IEN | M3)},				/* gpio_158 - spi_nirq */
+	{USBB2_ULPITLL_DIR, (PTU | IEN | M3)},				/* gpio_159 - bt_nreset */
+	{USBB2_ULPITLL_NXT, (PTU | IEN | M3)},				/* gpio_160 - audio_pwron*/
+	{USBB2_ULPITLL_DAT0, (PTU | IEN | M3)},				/* gpio_161 - bid_0 */
+	{USBB2_ULPITLL_DAT1, (PTU | IEN | M3)},				/* gpio_162 - bid_1 */
+	{USBB2_ULPITLL_DAT2, (PTU | IEN | M3)},				/* gpio_163 - bid_2 */
+	{USBB2_ULPITLL_DAT3, (PTU | IEN | M3)},				/* gpio_164 - bid_3 */
+	{USBB2_ULPITLL_DAT4, (PTU | IEN | M3)},				/* gpio_165 - bid_4 */
+	{USBB2_ULPITLL_DAT5, (PTU | IEN | M3)},				/* gpio_166 - ts_irq*/
+	{USBB2_ULPITLL_DAT6, (PTU | IEN | M3)},				/* gpio_167 - gps_pps */
+	{USBB2_ULPITLL_DAT7, (PTU | IEN | M3)},				/* gpio_168 */
+	{USBB2_HSIC_DATA, (PTU | IEN | M3)},				/* gpio_169 */
+	{USBB2_HSIC_STROBE, (PTU | IEN | M3)},				/* gpio_170 */
+	{UNIPRO_TX1, (PTU | IEN | M3)},					/* gpio_173 */
+	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
+	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
+	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
+	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
+	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_BOOT0, (M0)},						/* sys_boot0 */
+	{SYS_BOOT1, (M0)},						/* sys_boot1 */
+	{SYS_BOOT2, (M0)},						/* sys_boot2 */
+	{SYS_BOOT3, (M0)},						/* sys_boot3 */
+	{SYS_BOOT4, (M0)},						/* sys_boot4 */
+	{SYS_BOOT5, (M0)},						/* sys_boot5 */
+	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
+	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
+	{DPM_EMU16, (PTU | IEN | M3)},					/* gpio_27 */
+	{DPM_EMU17, (PTU | IEN | M3)},					/* gpio_28 */
+	{DPM_EMU18, (PTU | IEN | M3)},					/* gpio_29 */
+	{DPM_EMU19, (PTU | IEN | M3)},					/* gpio_30 */
+};
+
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+	{PAD1_FREF_XTAL_IN, (M0)},					/* fref_xtal_in  */
+	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M7)},					/* safe mode */
+	{PAD1_FREF_CLK3_REQ, M7},					/* safe mode */
+	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
+	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (M0)},						/* sys_boot6 */
+	{PAD1_SYS_BOOT7, (M0)},						/* sys_boot7 */
+};
+
+
+#endif /* _DUOVERO_MUX_DATA_H_ */
@@ -362,6 +362,7 @@
 Active  arm         armv7          omap3       ti              evm                 omap3_evm_quick_nand                  -                                                                                                                                 -
 Active  arm         armv7          omap3       ti              sdp3430             omap3_sdp3430                         -                                                                                                                                 Nishanth Menon <nm@ti.com>
 Active  arm         armv7          omap3       timll           devkit8000          devkit8000                            -                                                                                                                                 Thomas Weber <weber@corscience.de>
+Active  arm         armv7          omap4       gumstix         duovero             duovero                               -                                                                                                                                 Ash Charles <ash@gumstix.com>
 Active  arm         armv7          omap4       ti              panda               omap4_panda                           -                                                                                                                                 Sricharan R <r.sricharan@ti.com>
 Active  arm         armv7          omap4       ti              sdp4430             omap4_sdp4430                         -                                                                                                                                 Sricharan R <r.sricharan@ti.com>
 Active  arm         armv7          omap5       ti              dra7xx              dra7xx_evm                            dra7xx_evm:CONS_INDEX=1                                                                                                           Lokesh Vutla <lokeshvutla@ti.com>
+/*
+ * (C) Copyright: 2013
+ * Gumstix, Inc - http://www.gumstix.com
+ * Maintainer: Ash Charles  <ash@gumstix.com>
+ *
+ * Configuration settings for the Gumstix DuoVero board.
+ * See omap4_common.h for OMAP4 common part
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_DUOVERO_H
+#define __CONFIG_DUOVERO_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_DUOVERO
+#define MACH_TYPE_OMAP4_DUOVERO              4097    /* Until the next sync */
+#define CONFIG_MACH_TYPE                MACH_TYPE_OMAP4_DUOVERO
+
+#include <configs/ti_omap4_common.h>
+
+#undef CONFIG_SPL_OS_BOOT
+
+#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"duovero # "
+
+/* USB UHH support options */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
+
+#define CONFIG_SYS_ENABLE_PADS_ALL
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE		0x2C000000
+
+/* GPIO */
+#define CONFIG_CMD_GPIO
+
+/* ENV related config options */
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#endif /* __CONFIG_DUOVERO_H */
@@ -109,9 +109,13 @@
 	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
 		"env import -t ${loadaddr} ${filesize}\0" \
 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
 		"run mmcargs; " \
 		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"uimageboot=echo Booting from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
 	"findfdt="\
 		"if test $board_name = sdp4430; then " \
 			"setenv fdtfile omap4-sdp.dtb; fi; " \
@@ -121,6 +125,8 @@
 			"setenv fdtfile omap4-panda-a4.dtb; fi;" \
 		"if test $board_name = panda-es; then " \
 			"setenv fdtfile omap4-panda-es.dtb; fi;" \
+		"if test $board_name = duovero; then " \
+			"setenv fdtfile omap4-duovero.dtb; fi;" \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree to use; fi; \0" \
 	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
@@ -143,6 +149,9 @@
 		"if run loadimage; then " \
 			"run loadfdt;" \
 			"run mmcboot; " \
+		"fi; " \
+		"if run loaduimage; then " \
+			"run uimageboot;" \
 		"fi; " \
 	"fi"
	1	+#
	2	+# (C) Copyright 2000, 2001, 2002
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# SPDX-License-Identifier: GPL-2.0+
	6	+#
	7	+
	8	+obj-y := duovero.o
	1	+/*
	2	+ * (C) Copyright 2013
	3	+ * Gumstix Inc. <www.gumstix.com>
	4	+ * Maintainer: Ash Charles <ash@gumstix.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+#include <common.h>
	9	+#include <netdev.h>
	10	+#include <asm/arch/sys_proto.h>
	11	+#include <asm/arch/mmc_host_def.h>
	12	+#include <twl6030.h>
	13	+#include <asm/emif.h>
	14	+#include <asm/arch/clock.h>
	15	+#include <asm/arch/gpio.h>
	16	+#include <asm/gpio.h>
	17	+
	18	+#include "duovero_mux_data.h"
	19	+
	20	+#define WIFI_EN 43
	21	+
	22	+#if defined(CONFIG_CMD_NET)
	23	+#define SMSC_NRESET 45
	24	+static void setup_net_chip(void);
	25	+#endif
	26	+
	27	+#ifdef CONFIG_USB_EHCI
	28	+#include <usb.h>
	29	+#include <asm/arch/ehci.h>
	30	+#include <asm/ehci-omap.h>
	31	+#endif
	32	+
	33	+DECLARE_GLOBAL_DATA_PTR;
	34	+
	35	+const struct omap_sysinfo sysinfo = {
	36	+ "Board: duovero\n"
	37	+};
	38	+
	39	+struct omap4_scrm_regs const scrm = (struct omap4_scrm_regs )0x4a30a000;
	40	+
	41	+/**
	42	+ * @brief board_init
	43	+ *
	44	+ * @return 0
	45	+ */
	46	+int board_init(void)
	47	+{
	48	+ gpmc_init();
	49	+
	50	+ gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO;
	51	+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	52	+
	53	+ return 0;
	54	+}
	55	+
	56	+/**
	57	+ * @brief misc_init_r - Configure board specific configurations
	58	+ * such as power configurations, ethernet initialization as phase2 of
	59	+ * boot sequence
	60	+ *
	61	+ * @return 0
	62	+ */
	63	+int misc_init_r(void)
	64	+{
	65	+ int ret = 0;
	66	+ u8 val;
	67	+
	68	+ /* wifi setup: first enable 32Khz clock from 6030 pmic */
	69	+ val = 0xe1;
	70	+ ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
	71	+ if (ret)
	72	+ printf("Failed to enable 32Khz clock to wifi module\n");
	73	+
	74	+ /* then setup WIFI_EN as an output pin and send reset pulse */
	75	+ if (!gpio_request(WIFI_EN, "")) {
	76	+ gpio_direction_output(WIFI_EN, 0);
	77	+ gpio_set_value(WIFI_EN, 1);
	78	+ udelay(1);
	79	+ gpio_set_value(WIFI_EN, 0);
	80	+ udelay(1);
	81	+ gpio_set_value(WIFI_EN, 1);
	82	+ }
	83	+
	84	+#if defined(CONFIG_CMD_NET)
	85	+ setup_net_chip();
	86	+#endif
	87	+ return 0;
	88	+}
	89	+
	90	+void set_muxconf_regs_essential(void)
	91	+{
	92	+ do_set_mux((*ctrl)->control_padconf_core_base,
	93	+ core_padconf_array_essential,
	94	+ sizeof(core_padconf_array_essential) /
	95	+ sizeof(struct pad_conf_entry));
	96	+
	97	+ do_set_mux((*ctrl)->control_padconf_wkup_base,
	98	+ wkup_padconf_array_essential,
	99	+ sizeof(wkup_padconf_array_essential) /
	100	+ sizeof(struct pad_conf_entry));
	101	+
	102	+ do_set_mux((*ctrl)->control_padconf_core_base,
	103	+ core_padconf_array_non_essential,
	104	+ sizeof(core_padconf_array_non_essential) /
	105	+ sizeof(struct pad_conf_entry));
	106	+
	107	+ do_set_mux((*ctrl)->control_padconf_wkup_base,
	108	+ wkup_padconf_array_non_essential,
	109	+ sizeof(wkup_padconf_array_non_essential) /
	110	+ sizeof(struct pad_conf_entry));
	111	+}
	112	+
	113	+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
	114	+int board_mmc_init(bd_t *bis)
	115	+{
	116	+ return omap_mmc_init(0, 0, 0, -1, -1);
	117	+}
	118	+#endif
	119	+
	120	+
	121	+#if defined(CONFIG_CMD_NET)
	122	+
	123	+#define GPMC_SIZE_16M 0xF
	124	+#define GPMC_BASEADDR_MASK 0x3F
	125	+#define GPMC_CS_ENABLE 0x1
	126	+
	127	+static void enable_gpmc_net_config(const u32 gpmc_config, struct gpmc_cs cs,
	128	+ u32 base, u32 size)
	129	+{
	130	+ writel(0, &cs->config7);
	131	+ sdelay(1000);
	132	+ /* Delay for settling */
	133	+ writel(gpmc_config[0], &cs->config1);
	134	+ writel(gpmc_config[1], &cs->config2);
	135	+ writel(gpmc_config[2], &cs->config3);
	136	+ writel(gpmc_config[3], &cs->config4);
	137	+ writel(gpmc_config[4], &cs->config5);
	138	+ writel(gpmc_config[5], &cs->config6);
	139	+
	140	+ /*
	141	+ * Enable the config. size is the CS size and goes in
	142	+ * bits 11:8. We set bit 6 to enable this CS and the base
	143	+ * address goes into bits 5:0.
	144	+ */
	145	+ writel((size << 8) \| (GPMC_CS_ENABLE << 6) \|
	146	+ ((base >> 24) & GPMC_BASEADDR_MASK),
	147	+ &cs->config7);
	148	+
	149	+ sdelay(2000);
	150	+}
	151	+
	152	+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
	153	+#define NET_LAN9221_GPMC_CONFIG1 0x2a001203
	154	+#define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
	155	+#define NET_LAN9221_GPMC_CONFIG3 0x00020200
	156	+#define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
	157	+#define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
	158	+#define NET_LAN9221_GPMC_CONFIG6 0x8a070707
	159	+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
	160	+
	161	+/* GPMC definitions for LAN9221 chips on expansion boards */
	162	+static const u32 gpmc_lan_config[] = {
	163	+ NET_LAN9221_GPMC_CONFIG1,
	164	+ NET_LAN9221_GPMC_CONFIG2,
	165	+ NET_LAN9221_GPMC_CONFIG3,
	166	+ NET_LAN9221_GPMC_CONFIG4,
	167	+ NET_LAN9221_GPMC_CONFIG5,
	168	+ NET_LAN9221_GPMC_CONFIG6,
	169	+ /CONFIG7- computed as params /
	170	+};
	171	+
	172	+/*
	173	+ * Routine: setup_net_chip
	174	+ * Description: Setting up the configuration GPMC registers specific to the
	175	+ * Ethernet hardware.
	176	+ */
	177	+static void setup_net_chip(void)
	178	+{
	179	+ enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
	180	+ GPMC_SIZE_16M);
	181	+
	182	+ /* Make GPIO SMSC_NRESET as output pin and send reset pulse */
	183	+ if (!gpio_request(SMSC_NRESET, "")) {
	184	+ gpio_direction_output(SMSC_NRESET, 0);
	185	+ gpio_set_value(SMSC_NRESET, 1);
	186	+ udelay(1);
	187	+ gpio_set_value(SMSC_NRESET, 0);
	188	+ udelay(1);
	189	+ gpio_set_value(SMSC_NRESET, 1);
	190	+ }
	191	+}
	192	+#endif
	193	+
	194	+int board_eth_init(bd_t *bis)
	195	+{
	196	+ int rc = 0;
	197	+#ifdef CONFIG_SMC911X
	198	+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	199	+#endif
	200	+ return rc;
	201	+}
	202	+
	203	+#ifdef CONFIG_USB_EHCI
	204	+
	205	+static struct omap_usbhs_board_data usbhs_bdata = {
	206	+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
	207	+ .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
	208	+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
	209	+};
	210	+
	211	+int ehci_hcd_init(int index, enum usb_init_type init,
	212	+ struct ehci_hccr hccr, struct ehci_hcor hcor)
	213	+{
	214	+ int ret;
	215	+ unsigned int utmi_clk;
	216	+ u32 auxclk, altclksrc;
	217	+
	218	+ /* Now we can enable our port clocks */
	219	+ utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
	220	+ utmi_clk \|= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
	221	+ setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
	222	+
	223	+ auxclk = readl(&scrm->auxclk3);
	224	+ /* Select sys_clk */
	225	+ auxclk &= ~AUXCLK_SRCSELECT_MASK;
	226	+ auxclk \|= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
	227	+ /* Set the divisor to 2 */
	228	+ auxclk &= ~AUXCLK_CLKDIV_MASK;
	229	+ auxclk \|= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
	230	+ /* Request auxilary clock #3 */
	231	+ auxclk \|= AUXCLK_ENABLE_MASK;
	232	+ writel(auxclk, &scrm->auxclk3);
	233	+
	234	+ altclksrc = readl(&scrm->altclksrc);
	235	+
	236	+ /* Activate alternate system clock supplier */
	237	+ altclksrc &= ~ALTCLKSRC_MODE_MASK;
	238	+ altclksrc \|= ALTCLKSRC_MODE_ACTIVE;
	239	+
	240	+ /* enable clocks */
	241	+ altclksrc \|= ALTCLKSRC_ENABLE_INT_MASK \| ALTCLKSRC_ENABLE_EXT_MASK;
	242	+
	243	+ writel(altclksrc, &scrm->altclksrc);
	244	+
	245	+ ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
	246	+ if (ret < 0)
	247	+ return ret;
	248	+
	249	+ return 0;
	250	+}
	251	+
	252	+int ehci_hcd_stop(int index)
	253	+{
	254	+ return omap_ehci_hcd_stop();
	255	+}
	256	+#endif
	257	+
	258	+/*
	259	+ * get_board_rev() - get board revision
	260	+ */
	261	+u32 get_board_rev(void)
	262	+{
	263	+ return 0x20;
	264	+}
	1	+/*
	2	+ * (C) Copyright 2012
	3	+ * Gumstix Incorporated, <www.gumstix.com>
	4	+ * Maintainer: Ash Charles <ash@gumstix.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+#ifndef _DUOVERO_MUX_DATA_H_
	9	+#define _DUOVERO_MUX_DATA_H_
	10	+
	11	+#include <asm/arch/mux_omap4.h>
	12	+
	13	+const struct pad_conf_entry core_padconf_array_essential[] = {
	14	+ {SDMMC1_CLK, (PTU \| OFF_EN \| OFF_OUT_PTD \| M0)}, /* sdmmc1_clk */
	15	+ {SDMMC1_CMD, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc1_cmd */
	16	+ {SDMMC1_DAT0, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc1_dat0 */
	17	+ {SDMMC1_DAT1, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc1_dat1 */
	18	+ {SDMMC1_DAT2, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc1_dat2 */
	19	+ {SDMMC1_DAT3, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc1_dat3 */
	20	+ {I2C1_SCL, (PTU \| IEN \| M0)}, /* i2c1_scl */
	21	+ {I2C1_SDA, (PTU \| IEN \| M0)}, /* i2c1_sda */
	22	+ {I2C2_SCL, (PTU \| IEN \| M0)}, /* i2c2_scl */
	23	+ {I2C2_SDA, (PTU \| IEN \| M0)}, /* i2c2_sda */
	24	+ {I2C3_SCL, (PTU \| IEN \| M0)}, /* i2c3_scl */
	25	+ {I2C3_SDA, (PTU \| IEN \| M0)}, /* i2c3_sda */
	26	+ {I2C4_SCL, (PTU \| IEN \| M0)}, /* i2c4_scl */
	27	+ {I2C4_SDA, (PTU \| IEN \| M0)}, /* i2c4_sda */
	28	+ {UART3_CTS_RCTX, (PTU \| IEN \| M0)}, /* uart3_tx */
	29	+ {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
	30	+ {UART3_RX_IRRX, (PTU \| IEN \| M0)}, /* uart3_rx */
	31	+ {UART3_TX_IRTX, (M0)} /* uart3_tx */
	32	+};
	33	+
	34	+const struct pad_conf_entry wkup_padconf_array_essential[] = {
	35	+ {PAD1_SR_SCL, (PTU \| IEN \| M0)}, /* sr_scl */
	36	+ {PAD0_SR_SDA, (PTU \| IEN \| M0)}, /* sr_sda */
	37	+ {PAD1_SYS_32K, (IEN \| M0)} /* sys_32k */
	38	+};
	39	+
	40	+const struct pad_conf_entry core_padconf_array_non_essential[] = {
	41	+ {GPMC_AD0, (PTU \| IEN \| M0)}, /* gpmc_ad0 */
	42	+ {GPMC_AD1, (PTU \| IEN \| M0)}, /* gpmc_ad1 */
	43	+ {GPMC_AD2, (PTU \| IEN \| M0)}, /* gpmc_ad2 */
	44	+ {GPMC_AD3, (PTU \| IEN \| M0)}, /* gpmc_ad3 */
	45	+ {GPMC_AD4, (PTU \| IEN \| M0)}, /* gpmc_ad4 */
	46	+ {GPMC_AD5, (PTU \| IEN \| M0)}, /* gpmc_ad5 */
	47	+ {GPMC_AD6, (PTU \| IEN \| M0)}, /* gpmc_ad6 */
	48	+ {GPMC_AD7, (PTU \| IEN \| M0)}, /* gpmc_ad7 */
	49	+ {GPMC_AD8, (PTU \| IEN \| M0)}, /* gpmc_ad8 */
	50	+ {GPMC_AD9, (PTU \| IEN \| M0)}, /* gpmc_ad9 */
	51	+ {GPMC_AD10, (PTU \| IEN \| M0)}, /* gpmc_ad10 */
	52	+ {GPMC_AD11, (PTU \| IEN \| M0)}, /* gpmc_ad11 */
	53	+ {GPMC_AD12, (PTU \| IEN \| M0)}, /* gpmc_ad12 */
	54	+ {GPMC_AD13, (PTU \| IEN \| M0)}, /* gpmc_ad13 */
	55	+ {GPMC_AD14, (PTU \| IEN \| M0)}, /* gpmc_ad14 */
	56	+ {GPMC_AD15, (PTU \| IEN \| M0)}, /* gpmc_ad15 */
	57	+ {GPMC_A16, (PTU \| IEN \| M3)}, /* gpio_40 */
	58	+ {GPMC_A17, (PTU \| IEN \| M3)}, /* gpio_41 - hdmi_ls_oe */
	59	+ {GPMC_A18, (PTU \| IEN \| M3)}, /* gpio_42 */
	60	+ {GPMC_A19, (PTU \| IEN \| M3)}, /* gpio_43 - wifi_en */
	61	+ {GPMC_A20, (PTU \| IEN \| M3)}, /* gpio_44 - eth_irq */
	62	+ {GPMC_A21, (PTU \| IEN \| M3)}, /* gpio_45 - eth_nreset */
	63	+ {GPMC_A22, (PTU \| IEN \| M3)}, /* gpio_46 - eth_pme */
	64	+ {GPMC_A23, (PTU \| IEN \| M3)}, /* gpio_47 */
	65	+ {GPMC_A24, (PTU \| IEN \| M3)}, /* gpio_48 - eth_mdix */
	66	+ {GPMC_A25, (PTU \| IEN \| M3)}, /* gpio_49 - bt_wakeup */
	67	+ {GPMC_NCS0, (PTU \| M0)}, /* gpmc_ncs0 */
	68	+ {GPMC_NCS1, (PTU \| M0)}, /* gpmc_ncs1 */
	69	+ {GPMC_NCS2, (PTU \| M0)}, /* gpmc_ncs2 */
	70	+ {GPMC_NCS3, (PTU \| IEN \| M3)}, /* gpio_53 */
	71	+ {C2C_DATA12, (PTU \| M0)}, /* gpmc_ncs4 */
	72	+ {C2C_DATA13, (PTU \| M0)}, /* gpmc_ncs5 - eth_cs */
	73	+ {GPMC_NWP, (PTU \| IEN \| M0)}, /* gpmc_nwp */
	74	+ {GPMC_CLK, (PTU \| IEN \| M0)}, /* gpmc_clk */
	75	+ {GPMC_NADV_ALE, (PTU \| M0)}, /* gpmc_nadv_ale */
	76	+ {GPMC_NBE0_CLE, (PTU \| M0)}, /* gpmc_nbe0_cle */
	77	+ {GPMC_NBE1, (PTU \| M0)}, /* gpmc_nbe1 */
	78	+ {GPMC_WAIT0, (PTU \| IEN \| M0)}, /* gpmc_wait0 */
	79	+ {GPMC_WAIT1, (PTU \| IEN \| M0)}, /* gpio_62 - usbh_nreset */
	80	+ {GPMC_NOE, (PTU \| M0)}, /* gpmc_noe */
	81	+ {GPMC_NWE, (PTU \| M0)}, /* gpmc_nwe */
	82	+ {HDMI_HPD, (PTD \| IEN \| M3)}, /* gpio_63 - hdmi_hpd */
	83	+ {HDMI_CEC, (PTU \| IEN \| M0)}, /* hdmi_cec */
	84	+ {HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */
	85	+ {HDMI_DDC_SDA, (IEN \| M0)}, /* hdmi_ddc_sda */
	86	+ {CSI21_DX0, (IEN \| M0)}, /* csi21_dx0 */
	87	+ {CSI21_DY0, (IEN \| M0)}, /* csi21_dy0 */
	88	+ {CSI21_DX1, (IEN \| M0)}, /* csi21_dx1 */
	89	+ {CSI21_DY1, (IEN \| M0)}, /* csi21_dy1 */
	90	+ {CSI21_DX2, (IEN \| M0)}, /* csi21_dx2 */
	91	+ {CSI21_DY2, (IEN \| M0)}, /* csi21_dy2 */
	92	+ {CSI21_DX3, (IEN \| M0)}, /* csi21_dx3 */
	93	+ {CSI21_DY3, (IEN \| M0)}, /* csi21_dy3 */
	94	+ {CSI21_DX4, (IEN \| M0)}, /* csi21_dx4 */
	95	+ {CSI21_DY4, (IEN \| M0)}, /* csi21_dy4 */
	96	+ {CSI22_DX0, (IEN \| M0)}, /* csi22_dx0 */
	97	+ {CSI22_DY0, (IEN \| M0)}, /* csi22_dy0 */
	98	+ {CSI22_DX1, (IEN \| M0)}, /* csi22_dx1 */
	99	+ {CSI22_DY1, (IEN \| M0)}, /* csi22_dy1 */
	100	+ {USBB1_ULPITLL_CLK, (PTD \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)},/* usbb1_ulpiphy_clk */
	101	+ {USBB1_ULPITLL_STP, (OFF_EN \| OFF_OUT_PTD \| M4)}, /* usbb1_ulpiphy_stp */
	102	+ {USBB1_ULPITLL_DIR, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dir */
	103	+ {USBB1_ULPITLL_NXT, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_nxt */
	104	+ {USBB1_ULPITLL_DAT0, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dat0 */
	105	+ {USBB1_ULPITLL_DAT1, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dat1 */
	106	+ {USBB1_ULPITLL_DAT2, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dat2 */
	107	+ {USBB1_ULPITLL_DAT3, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dat3 */
	108	+ {USBB1_ULPITLL_DAT4, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dat4 */
	109	+ {USBB1_ULPITLL_DAT5, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dat5 */
	110	+ {USBB1_ULPITLL_DAT6, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dat6 */
	111	+ {USBB1_ULPITLL_DAT7, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M4)}, /* usbb1_ulpiphy_dat7 */
	112	+ {USBB1_HSIC_DATA, (PTU \| IEN \| M3)}, /* gpio_96 - usbh_cpen */
	113	+ {USBB1_HSIC_STROBE, (PTU \| IEN \| M3)}, /* gpio_97 - usbh_reset */
	114	+ {ABE_MCBSP2_CLKX, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* abe_mcbsp2_clkx */
	115	+ {ABE_MCBSP2_DR, (IEN \| OFF_EN \| OFF_OUT_PTD \| M0)}, /* abe_mcbsp2_dr */
	116	+ {ABE_MCBSP2_DX, (OFF_EN \| OFF_OUT_PTD \| M0)}, /* abe_mcbsp2_dx */
	117	+ {ABE_MCBSP2_FSX, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* abe_mcbsp2_fsx */
	118	+ {ABE_PDM_UL_DATA, (PTD \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* abe_pdm_ul_data */
	119	+ {ABE_PDM_DL_DATA, (PTD \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* abe_pdm_dl_data */
	120	+ {ABE_PDM_FRAME, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* abe_pdm_frame */
	121	+ {ABE_PDM_LB_CLK, (PTD \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* abe_pdm_lb_clk */
	122	+ {ABE_CLKS, (PTD \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* abe_clks */
	123	+ {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
	124	+ {ABE_DMIC_DIN1, (IEN \| M0)}, /* abe_dmic_din1 */
	125	+ {ABE_DMIC_DIN2, (IEN \| M0)}, /* abe_dmic_din2 */
	126	+ {ABE_DMIC_DIN3, (IEN \| M0)}, /* abe_dmic_din3 */
	127	+ {UART2_CTS, (PTU \| IEN \| M0)}, /* uart2_cts */
	128	+ {UART2_RTS, (M0)}, /* uart2_rts */
	129	+ {UART2_RX, (PTU \| IEN \| M0)}, /* uart2_rx */
	130	+ {UART2_TX, (M0)}, /* uart2_tx */
	131	+ {HDQ_SIO, (M0)}, /* hdq-sio */
	132	+ {MCSPI1_CLK, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi1_clk */
	133	+ {MCSPI1_SOMI, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi1_somi */
	134	+ {MCSPI1_SIMO, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi1_simo */
	135	+ {MCSPI1_CS0, (PTD \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi1_cs0 */
	136	+ {MCSPI1_CS1, (PTD \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi1_cs1 */
	137	+ {SDMMC5_CLK, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc5_clk */
	138	+ {SDMMC5_CMD, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc5_cmd */
	139	+ {SDMMC5_DAT0, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc5_dat0 */
	140	+ {SDMMC5_DAT1, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc5_dat1 */
	141	+ {SDMMC5_DAT2, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc5_dat2 */
	142	+ {SDMMC5_DAT3, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* sdmmc5_dat3 */
	143	+ {MCSPI4_CLK, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi4_clk */
	144	+ {MCSPI4_SIMO, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi4_simo */
	145	+ {MCSPI4_SOMI, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi4_somi */
	146	+ {MCSPI4_CS0, (PTD \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* mcspi4_cs0 */
	147	+ {UART4_RX, (IEN \| PTU \| M0)}, /* uart4_rx */
	148	+ {UART4_TX, (M0)}, /* uart4_tx */
	149	+ {USBB2_ULPITLL_CLK, (PTU \| IEN \| M3)}, /* gpio_157 - start_adc */
	150	+ {USBB2_ULPITLL_STP, (PTU \| IEN \| M3)}, /* gpio_158 - spi_nirq */
	151	+ {USBB2_ULPITLL_DIR, (PTU \| IEN \| M3)}, /* gpio_159 - bt_nreset */
	152	+ {USBB2_ULPITLL_NXT, (PTU \| IEN \| M3)}, /* gpio_160 - audio_pwron*/
	153	+ {USBB2_ULPITLL_DAT0, (PTU \| IEN \| M3)}, /* gpio_161 - bid_0 */
	154	+ {USBB2_ULPITLL_DAT1, (PTU \| IEN \| M3)}, /* gpio_162 - bid_1 */
	155	+ {USBB2_ULPITLL_DAT2, (PTU \| IEN \| M3)}, /* gpio_163 - bid_2 */
	156	+ {USBB2_ULPITLL_DAT3, (PTU \| IEN \| M3)}, /* gpio_164 - bid_3 */
	157	+ {USBB2_ULPITLL_DAT4, (PTU \| IEN \| M3)}, /* gpio_165 - bid_4 */
	158	+ {USBB2_ULPITLL_DAT5, (PTU \| IEN \| M3)}, /* gpio_166 - ts_irq*/
	159	+ {USBB2_ULPITLL_DAT6, (PTU \| IEN \| M3)}, /* gpio_167 - gps_pps */
	160	+ {USBB2_ULPITLL_DAT7, (PTU \| IEN \| M3)}, /* gpio_168 */
	161	+ {USBB2_HSIC_DATA, (PTU \| IEN \| M3)}, /* gpio_169 */
	162	+ {USBB2_HSIC_STROBE, (PTU \| IEN \| M3)}, /* gpio_170 */
	163	+ {UNIPRO_TX1, (PTU \| IEN \| M3)}, /* gpio_173 */
	164	+ {USBA0_OTG_CE, (PTD \| OFF_EN \| OFF_PD \| OFF_OUT_PTD \| M0)}, /* usba0_otg_ce */
	165	+ {USBA0_OTG_DP, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* usba0_otg_dp */
	166	+ {USBA0_OTG_DM, (IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, /* usba0_otg_dm */
	167	+ {SYS_NIRQ1, (PTU \| IEN \| M0)}, /* sys_nirq1 */
	168	+ {SYS_NIRQ2, (PTU \| IEN \| M0)}, /* sys_nirq2 */
	169	+ {SYS_BOOT0, (M0)}, /* sys_boot0 */
	170	+ {SYS_BOOT1, (M0)}, /* sys_boot1 */
	171	+ {SYS_BOOT2, (M0)}, /* sys_boot2 */
	172	+ {SYS_BOOT3, (M0)}, /* sys_boot3 */
	173	+ {SYS_BOOT4, (M0)}, /* sys_boot4 */
	174	+ {SYS_BOOT5, (M0)}, /* sys_boot5 */
	175	+ {DPM_EMU0, (IEN \| M0)}, /* dpm_emu0 */
	176	+ {DPM_EMU1, (IEN \| M0)}, /* dpm_emu1 */
	177	+ {DPM_EMU16, (PTU \| IEN \| M3)}, /* gpio_27 */
	178	+ {DPM_EMU17, (PTU \| IEN \| M3)}, /* gpio_28 */
	179	+ {DPM_EMU18, (PTU \| IEN \| M3)}, /* gpio_29 */
	180	+ {DPM_EMU19, (PTU \| IEN \| M3)}, /* gpio_30 */
	181	+};
	182	+
	183	+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
	184	+ {PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */
	185	+ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
	186	+ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
	187	+ {PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */
	188	+ {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
	189	+ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
	190	+ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
	191	+ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
	192	+ {PAD0_SYS_PWR_REQ, (PTU \| M0)}, /* sys_pwr_req */
	193	+ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
	194	+ {PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */
	195	+ {PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */
	196	+};
	197	+
	198	+
	199	+#endif /* _DUOVERO_MUX_DATA_H_ */
...	...	@@ -362,6 +362,7 @@
362	362	Active arm armv7 omap3 ti evm omap3_evm_quick_nand - -
363	363	Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com>
364	364	Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de>
	365	+Active arm armv7 omap4 gumstix duovero duovero - Ash Charles <ash@gumstix.com>
365	366	Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
366	367	Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
367	368	Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
	1	+/*
	2	+ * (C) Copyright: 2013
	3	+ * Gumstix, Inc - http://www.gumstix.com
	4	+ * Maintainer: Ash Charles <ash@gumstix.com>
	5	+ *
	6	+ * Configuration settings for the Gumstix DuoVero board.
	7	+ * See omap4_common.h for OMAP4 common part
	8	+ *
	9	+ * SPDX-License-Identifier: GPL-2.0+
	10	+ */
	11	+
	12	+#ifndef __CONFIG_DUOVERO_H
	13	+#define __CONFIG_DUOVERO_H
	14	+
	15	+/*
	16	+ * High Level Configuration Options
	17	+ */
	18	+#define CONFIG_DUOVERO
	19	+#define MACH_TYPE_OMAP4_DUOVERO 4097 /* Until the next sync */
	20	+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP4_DUOVERO
	21	+
	22	+#include <configs/ti_omap4_common.h>
	23	+
	24	+#undef CONFIG_SPL_OS_BOOT
	25	+
	26	+#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
	27	+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
	28	+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
	29	+
	30	+#undef CONFIG_SYS_PROMPT
	31	+#define CONFIG_SYS_PROMPT "duovero # "
	32	+
	33	+/* USB UHH support options */
	34	+#define CONFIG_CMD_USB
	35	+#define CONFIG_USB_HOST
	36	+#define CONFIG_USB_EHCI
	37	+#define CONFIG_USB_EHCI_OMAP
	38	+#define CONFIG_USB_STORAGE
	39	+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
	40	+
	41	+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
	42	+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
	43	+
	44	+#define CONFIG_SYS_ENABLE_PADS_ALL
	45	+
	46	+#define CONFIG_CMD_PING
	47	+#define CONFIG_CMD_DHCP
	48	+#define CONFIG_CMD_NET
	49	+
	50	+#define CONFIG_SMC911X
	51	+#define CONFIG_SMC911X_32_BIT
	52	+#define CONFIG_SMC911X_BASE 0x2C000000
	53	+
	54	+/* GPIO */
	55	+#define CONFIG_CMD_GPIO
	56	+
	57	+/* ENV related config options */
	58	+#define CONFIG_ENV_IS_NOWHERE
	59	+
	60	+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	61	+
	62	+#endif /* __CONFIG_DUOVERO_H */
...	...	@@ -109,9 +109,13 @@
109	109	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
110	110	"env import -t ${loadaddr} ${filesize}\0" \
111	111	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
	112	+ "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
112	113	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
113	114	"run mmcargs; " \
114	115	"bootz ${loadaddr} - ${fdtaddr}\0" \
	116	+ "uimageboot=echo Booting from mmc${mmcdev} ...; " \
	117	+ "run mmcargs; " \
	118	+ "bootm ${loadaddr}\0" \
115	119	"findfdt="\
116	120	"if test $board_name = sdp4430; then " \
117	121	"setenv fdtfile omap4-sdp.dtb; fi; " \
...	...	@@ -121,6 +125,8 @@
121	125	"setenv fdtfile omap4-panda-a4.dtb; fi;" \
122	126	"if test $board_name = panda-es; then " \
123	127	"setenv fdtfile omap4-panda-es.dtb; fi;" \
	128	+ "if test $board_name = duovero; then " \
	129	+ "setenv fdtfile omap4-duovero.dtb; fi;" \
124	130	"if test $fdtfile = undefined; then " \
125	131	"echo WARNING: Could not determine device tree to use; fi; \0" \
126	132	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
...	...	@@ -143,6 +149,9 @@
143	149	"if run loadimage; then " \
144	150	"run loadfdt;" \
145	151	"run mmcboot; " \
	152	+ "fi; " \
	153	+ "if run loaduimage; then " \
	154	+ "run uimageboot;" \
146	155	"fi; " \
147	156	"fi"
148	157