20 Nov, 2018
1 commit
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Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.Signed-off-by: Bai Ping
Reviewed-by: Ye Li
Tested-by: Robby Cai
03 Nov, 2018
1 commit
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Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.Signed-off-by: Bai Ping
12 Oct, 2018
1 commit
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Update the refresh_mode setting. Clear the RFSHCTL3.refresh_mode bit
to set it to normal_mode.Signed-off-by: Bai Ping
Reviewed-by: Ye Li
01 Oct, 2018
2 commits
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Optimize the DDR4 init flow. Split the common flow
with the DDR specific timing config. So the common
flow can be reused.Signed-off-by: Bai Ping
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For LPDDR4 or DDR4, the ddr phy train flow is the same.
So rename the 'lpddr4_ddrphy_train.c' to 'ddrphy_train.c'.
make it more common for reuse and move it to driver/ddr/imx8m/.Signed-off-by: Bai Ping
07 Aug, 2018
1 commit
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Android build use different tool chain(gcc 4.9) with yocto(gcc 6.2),
'for' loop initial declarations are not supported in C90, define the
variable first before use it.Test: build pass for imx8mm_evk.
Change-Id: Idf9a9f21626a02e2e679d2e74410378cd143c3f1
Signed-off-by: Luo Ji
06 Aug, 2018
1 commit
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the dram init is board related. But there is still some common
part can be reused on different board. The basic flow is common
for all the board. only the DDRC and DDR PHY config register setting
is different on different board. So extract the LPDDR4 init common
flow to make it more generic. baord level only need to provide
the DDRC and PHY config register parameter to the common code to finish
the dram init.the same method can be use for DDR4. will be added later.
Signed-off-by: Bai Ping
(cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1)
15 Feb, 2018
1 commit
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Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4.Signed-off-by: Tom Rini
10 Feb, 2018
1 commit
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To make this driver easier to be reused, dual-license DDR driver.
Signed-off-by: York Sun
CC: Simon Glass
CC: Tom Rini
CC: Heinrich Schuchardt
CC: Thomas Schaefer
CC: Masahiro Yamada
CC: Robert P. J. Day
CC: Alexander Merkle
CC: Joakim Tjernlund
CC: Curt Brune
CC: Valentin Longchamp
CC: Wolfgang Denk
CC: Anatolij Gustschin
CC: Ira W. Snyder
CC: Marek Vasut
CC: Kyle Moffett
CC: Sebastien Carlier
CC: Stefan Roese
CC: Peter Tyser
CC: Paul Gortmaker
CC: Peter Tyser
CC: Jean-Christophe PLAGNIOL-VILLARD
31 Jan, 2018
6 commits
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Variable "row_density" is no longer used. Drop it from DIMM structure.
Signed-off-by: York Sun
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DDR controllers always use binding register to determine the memory
space to perform data initialization. In case of controller interleaving,
the space is doubled, resulting twice long wait. It wasn't too bad until
the memory capacity increases. To reduce the wait time, reduce the
binding space to half and restore it after data initialization.
Three-way interleaving is no longer used and is removed.Signed-off-by: York Sun
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DDR4 RDIMM has some information in SPD to be used to calculate the
control words for register chip. The rest can be found from JEDEC
spec DDR4RCD02.Signed-off-by: York Sun
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On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.Signed-off-by: York Sun
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Wrong field was masked in this workaround due to wrong endianness. The
impacted SoCs have big-endian.Signed-off-by: York Sun
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For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.Signed-off-by: York Sun
28 Jan, 2018
1 commit
26 Jan, 2018
1 commit
25 Jan, 2018
1 commit
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This driver has been using printf() including filename since it was
added. Convert to using debug() instead.Signed-off-by: Simon Goldschmidt
24 Jan, 2018
2 commits
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wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Jagan Teki -
Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCsSigned-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
Reviewed-by: York Sun
19 Jan, 2018
4 commits
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Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f
instead of 0xf. Rather than checking the read sample delay for all DDR
chip selects use the values for the chip selects that are actually
configured. Finally continue searching for the max_phase value even if the
current read_sample is the same as the max_read_sample.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
The ternary operation had the HIGH/LOW values the
wrong way round. Update it to use the correct value.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese
11 Sep, 2017
1 commit
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LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.Signed-off-by: Alison Wang
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Signed-off-by: Raghav Dogra
Signed-off-by: Shaohui Xie
[YS: Revised commit message]
Reviewed-by: York Sun
16 Aug, 2017
1 commit
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We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.Suggested-by: Wolfgang Denk
Signed-off-by: Simon Glass
14 Aug, 2017
2 commits
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Remove superfluous self assignements.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Stefan Roese -
Assigning dev_num to itself is superfluous.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Stefan Roese
12 Jul, 2017
1 commit
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The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
from the number of CSs
HWS_TIM_1T - enforce 1t
HWS_TIM_2T - enforce 2tThis patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.Signed-off-by: Marek Behun
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese
16 Jun, 2017
1 commit
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Signed-off-by: Masahiro Yamada
13 Jun, 2017
1 commit
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Fix compiling error of "no member named 'taamin_ps'" for DDR2.
Signed-off-by: York Sun
06 Jun, 2017
2 commits
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We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.Signed-off-by: Simon Glass
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The declarations should not be in common.h. Move them to the arch-specific
headers.Signed-off-by: Simon Glass
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini
18 Apr, 2017
3 commits
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(pdimm[0].data_width >= 32) || (pdimm[0].data_width
Reviewed-by: Tom Rini
Reviewed-by: York Sun -
Depending on DDR configuration, gcc-6.x will show up unused-const-
variable messages. Use __maybe_unused specifier for all dynamic_odt
variable definitions to remove these warnings.Memory footprint will not increase as gcc will optimize out unused
constants.Signed-off-by: Thomas Schaefer
Signed-off-by: York Sun
14 Apr, 2017
2 commits
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Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
13 Apr, 2017
1 commit
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This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.Signed-off-by: Simon Glass
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini
06 Apr, 2017
1 commit
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At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese