27 Apr, 2018
1 commit
-
- one lane pcie gen2 link is okay, the cfg space
of the rc/ep can be accessed.
rc cfg base 0x5f00_0000. ep cfg base 0x6000_0000
- limit to gen2 speed
- mask the wait of eq3 finish, because it is used
for gen3.
- use pcie_ctrla_init_rc() to do the initialization
of the pciea controller
- setup the common pcie codes in pcie_imx8x.c, separate
the different soc speicifed initialization codes into
their own pcie/board codes, move the macro definitions
into the new header file imx8_hsio.h.
- i.MX8QXP only have PCIe Control B. Enable PORT B at default.
i.MX8QM needs to set CONFIG_IMX_PCIEB to enable PORT B.
- Disable the LTSSM when link is down.Signed-off-by: Frank Li
Signed-off-by: Richard Zhu
Signed-off-by: Shenwei Wang
Signed-off-by: Ye Li
(cherry picked from commit 03141c2b955ce6034f06e701126aea1493dc2b4b)
