23 Jun, 2019
1 commit
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Converted to use fsl_esdhc_imx for i.MX platforms.
Signed-off-by: Yangbo Lu
Tested-by: Steffen Dirkwinkel
Reviewed-by: Peng Fan
Reviewed-by: Lukasz Majewski
Reviewed-by: Martyn Welch
Acked-by: Jason Liu
26 Apr, 2019
1 commit
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Port for the DART-6UL Evaluation Kit SBC. Based on the variscite
DART-6UL iMX6ULL SoM.CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
In: serial@02020000
Out: serial@02020000
Err: serial@02020000
Net: FEC0Working:
- Eth0
- i2c
- MMC/SD
- eMMC
- USB host
- UART 1Note: LCDIF porting needs DM_VIDEO
https://lists.denx.de/pipermail/u-boot/2019-April/365506.htmlSigned-off-by: Parthiban Nallathambi