24 May, 2019
4 commits
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If a pad is not owned by current partition we should not set its
pinmux.Signed-off-by: Ye Li
(cherry picked from commit 547636514f8ae8b456f2351bc84cb7fb7b5fa3f3) -
When selecting imx8 pinctrl, we don't need to select DEVRES
Signed-off-by: Ye Li
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The CONFIG_DEVRES is not a necessary config for pinctrl. We decouple the
dependence from the kconfig. So the DEVRES is not default enabled.When using DWC3 gadget driver, without enabling gadget DM driver, the calling
to devm_kzalloc will cause crash if CONFIG_DEVRES is set.Signed-off-by: Ye Li
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Update pinctrl driver for i.MX8 platform (QM/QXP) to add compatible string
for iMX8QM. So the driver can parse the iomuxc settings from iMX8QM DTB
and set them through IPC to SCU.Signed-off-by: Ye Li
29 Mar, 2019
1 commit
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There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.Signed-off-by: David Wu
13 Mar, 2019
1 commit
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Add i.mx8m pinctrl driver.
Signed-off-by: Peng Fan
04 Mar, 2019
9 commits
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Since the datasheet Rev.1.00 has an error about the USB ID pin name,
this patch revises it.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50,
the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected,
and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is
selected.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
According to the R-Car Gen3 Hardware Manual Rev.1.50, the MOD_SEL0
bit16 is set to 0 when NFALE_A and NFRB_N_A pin functions are
selected.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
According to the R-Car Gen3 Hardware Manual Rev 1.50, the MOD_SEL0
bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are
selected.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR /
MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was
confirmed in the R-Car Gen3 Hardware Manual Rev.1.50.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22]
of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
This patch removes CC5_OSCOUT assignment of IP17[3:0] of r8a7795
/ r8a7796 / r8a77965. This information was confirmed in the R-Car
Gen3 Hardware Manual Rev.1.50.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
This patch fixes to the correct names, and "_" is not include after
"adg" for r8a7795/r8a7796/r8a77965. This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
This patch is change the bit assignment of "HDMI1_CEC" to "GP7_03",
and "HDMI0_CEC" to "GP7_02". This information was confirmed in the
R-Car Gen3 Hardware Manual Rev.1.50.Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
25 Feb, 2019
1 commit
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Drop per SoC def_bool on each driver, since this is now implied by
SoC Kconfig option instead.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
01 Feb, 2019
5 commits
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After the merge of the new, generic pinctrl-code, the include for
rockchip/Kconfig was missing. Add it here, so we can select the
pinctrl-driver for SPL.Signed-off-by: Philipp Tomsich
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To make adding new subdirectories easier, let's enforce alphabetical
ordering of the includes of Kconfig files in the respective
subdirectories.Signed-off-by: Philipp Tomsich
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If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.Signed-off-by: David Wu
Reviewed-by: Simon Glass
Tested-by: Simon Glass
Reviewed-by: Kever Yang
Reviewed-by: Philipp Tomsich -
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.Signed-off-by: David Wu
Acked-by: Heiko Stuebner
Reviewed-by: Kever Yang
Reviewed-by: Philipp Tomsich -
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.pySigned-off-by: Simon Glass
Reviewed-by: Philipp Tomsich
30 Jan, 2019
1 commit
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For 2019.04
29 Jan, 2019
2 commits
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Adding pinconf support is necessary to enable boot from SPI
without breaking the eMMC. When booting from SPI, the ROM code
leave pull downs on the eMMC pad.We need to set pinconf provided in DT to solve this
Signed-off-by: Jerome Brunet
Signed-off-by: Neil Armstrong
[narmstrong: added missing comma in pinctrl-meson-axg-pmx.c] -
The pinctrl supports to set any bit in input register on iMX6 if
the MSB of input value is 0xff. But the driver uses signed int for
input value, so when executing the codes below, it won't meet.
Because this is arithmetic right shift.if (input_val >> 24 == 0xff)
Fix the issue by changing the input_val, config_val and mux_mode to u32.
Signed-off-by: Ye Li
Reviewed-by: Fugang Duan
Reviewed-by: Peng Fan
24 Jan, 2019
2 commits
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The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.Signed-off-by: Horatiu Vultur
Reviewed-by: Daniel Schwierzeck -
The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.Reviewed-by: Daniel Schwierzeck
Signed-off-by: Horatiu Vultur
18 Jan, 2019
1 commit
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Signed-off-by: Chris Packham
Reviewed-by: Simon Glass
16 Jan, 2019
1 commit
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The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common
to support new numbe of pins and remove any platform dependency from
mscc-common.Signed-off-by: Horatiu Vultur
11 Jan, 2019
1 commit
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This reverts commit a7f4b4b344396590845e6552c82829ef68ef9f89.
As reported by Alex Kiernan the above optimization introduces a
regression in the below use case where:1. Device has defined 'u-boot,dm-spl' property (@ eMMC DTS node)
2. The device downloads its MLO/SPL via UART (not eMMC - the eMMC pinmux
pins are NOT probed/configured in MLO/SPL).3. The loaded via UART MLO/SPL wants to load Linux from eMMC. In this case
the DM core and pinctrl uclass checks 'u-boot,dm-spl' and don't
configure pins (as it thinks that those were initialized in MLO/SPL).As we are very close to release - please revert this commit.
Reported-by: Alex Kiernan
Signed-off-by: Lukasz Majewski
Reviewed-by: Simon Glass
06 Jan, 2019
1 commit
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Braces around the error-case for rk3399_pinctrl_set_pin_pupd lead to
an unconditional (and unintended) return from the function without it
ever setting pin-configurations.Fix it.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
03 Jan, 2019
3 commits
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This patch adds a Kconfig option to enable the full pinctrl driver
for the RK3399. This flag needs to be enabed in order to get the
features of the full pinctrl driver compiled in (i.e. a .set_state()
callback).Signed-off-by: Christoph Muellner
Reviewed-by: Philipp Tomsich -
The current pinctrl driver for the RK3399 has a range of qulity issues.
E.g. it only implements the .set_state_simple() callback, it
does not parse the available pinctrl information from the DTS
(instead uses hardcoded values), is not flexible enough to cover
devices without 'interrupt' field in the DTS (e.g. PWM),
is not written generic enough to make code reusable among other
rockchip SoCs...This patch addresses these issues by reimplementing the whole driver
from scratch using the .set_state() callback.
The new implementation covers all featurese of the old code
(i.e. it supports pinmuxing and pullup/pulldown configuration).This patch has been tested on a RK3399-Q7 SoM (Puma).
Signed-off-by: Christoph Muellner
Reviewed-by: Philipp Tomsich -
pinctrl_decode_pin_config_dm() is basically a feature-equivalent
implementation of pinctrl_decode_pin_config(), which operates
on struct udevice devices and uses the dev_read_*() API.Signed-off-by: Christoph Muellner
Reviewed-by: Philipp Tomsich
01 Jan, 2019
2 commits
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imx for 2019.01
- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x -
This implementation comply with other iMX devices pinctrl drivers already
available in U-boot.Signed-off-by: Lukasz Majewski
27 Dec, 2018
1 commit
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This commit prevents from re-configuring pins if those were configured
before relocation.Some pins - like UART or DDR must be setup before relocation
(as they have 'u-boot,dm-pre-reloc' property set in DTS). Without this
change, those pins are re-configured after relocation (pre_reloc_only = 0,
so we do not "continue").
Such behavior may be a problem for DDR PAD configuration, as they might
be already leveled/tuned with original setup).Signed-off-by: Lukasz Majewski
19 Dec, 2018
1 commit
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This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).For Ocelot and Luton the controller is the same, only the pins to program
differ.Signed-off-by: Gregory CLEMENT
Reviewed-by: Daniel Schwierzeck
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC]
Signed-off-by: Daniel Schwierzeck
08 Dec, 2018
1 commit
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Two fixes for the Amlogic Pinctrl driver :
- bad usage of clrsetbits_le32
- bad pin definition for AXG Family
07 Dec, 2018
2 commits
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Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must
be updated.stm32_pinctrl_get_gpio_dev() returns from a given pin selectors
the corresponding bank gpio device and the gpio_offset inside this
gpio bank.Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev.
Signed-off-by: Patrice Chotard
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Move gpio_dev list filling outside probe() to speed-up U-boot
boot sequence execution. This list is populated only when needed.Signed-off-by: Patrice Chotard
