05 Sep, 2013
1 commit
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Conflicts:
drivers/serial/serial.cThe conflict above was a trivial case of adding one init
function in each branch, and manually resolved in merge.
23 Aug, 2013
1 commit
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Enable support for high-capacity eMMC and MMC cards. The MXS MMC
driver has no problem with those.Signed-off-by: Marek Vasut
Signed-off-by: Amaury Pouly
Cc: Andy Fleming
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Otavio Salvador
Reviewed-by: Otavio Salvador
21 Aug, 2013
2 commits
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This patch cleans up license header in these files:
board/freescale/p1022ds/spl.c
drivers/mmc/fsl_esdhc_spl.c
drivers/mtd/spi/fsl_espi_spl.cSigned-off-by: York Sun
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The code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
ddr spd code can get the interleaving mode setting in env. It loads
final uboot image from offset 96KB.
* final uboot image, size is variable depends on the functions enabled.Signed-off-by: Ying Zhang
Acked-by: York Sun
25 Jul, 2013
1 commit
24 Jul, 2013
2 commits
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini -
The FTSDC010_DCR_FIFO_RST symbol is conditionally
defined in and it is available
available when CONFIG_FTSDC010_SDIO is enabled.However the actual driver code unconditionally uses
the FTSDC010_DCR_FIFO_RST constant and this causes
build error if CONFIG_FTSDC010_SDIO is not enabled.The following error happens when compiling for the
adp-ag101 board:ftsdc010_mci.c: In function 'ftsdc010_request':
ftsdc010_mci.c:178: error: 'FTSDC010_DCR_FIFO_RST' undeclared (first use in this function)
ftsdc010_mci.c:178: error: (Each undeclared identifier is reported only once
ftsdc010_mci.c:178: error: for each function it appears in.)The patch ensures that the FTSDC010_DCR_FIFO_RST
symbol gets used only if CONFIG_FTSDC010_SDIO is
defined.Compile tested only.
Cc: Kuo-Jung Su
Cc: Macpaul Lin
Signed-off-by: Gabor Juhos
Reviewed-by: Kuo-Jung Su
17 Jul, 2013
3 commits
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Dealing with the sys ctrl register should touch only the
relevant bits and not accidently the whole register. On i.MX6,
the sys control register contains bits which shouldn't be reset to
0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]).Do this by read/modify/write instead of just a 32bit write.
Signed-off-by: Dirk Behme
Acked-by: Stefano Babic
Signed-off-by: Andy Fleming -
1. No contents of "asm/arch/clk.h" is used within "dw_mmc.c".
2. If arch doesn't have "asm/arch/clk.h" driver won't build.Without mentioned inclusion dw_mmc driver could be built for arches
other than ARM. For ARM driver still builds without it.Signed-off-by: Alexey Brodkin
Cc: Mischa Jonker
Cc: Andy Fleming
Cc: Rajeshwari Shinde
Cc: Amar
Cc: Minkyu Kang
Cc: Jaehoon Chung
Signed-off-by: Andy Fleming -
Fill the right command type when using CMD12 to stop data transfer.
Signed-off-by: Haijun Zhang
CC: Fleming Andrew-AFLEMING
CC: Scott Wood
Signed-off-by: Andy Fleming
26 Jun, 2013
1 commit
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With CONFIG_SYS_64BIT_LBA, lbaint_t gets defined as a 64-bit type,
which is required to represent block numbers for storage devices that
exceed 2TiB (the block size usually is 512B), e.g. recent hard drives.For some obscure reason, the current U-Boot code uses lbaint_t for the
number of blocks to read (a rather optimistic estimation of how RAM
sizes will evolve), but not for the starting address. Trying to access
blocks beyond the 2TiB boundary will simply wrap around and read a
block within the 0..2TiB range.We now use lbaint_t for block start addresses, too. This required
changes to all block drivers as the signature of block_read(),
block_write() and block_erase() in block_dev_desc_t changed.Signed-off-by: Sascha Silbe
22 Jun, 2013
1 commit
19 Jun, 2013
1 commit
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Conflicts:
spl/Makefile
17 Jun, 2013
1 commit
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Current DWMMC driver used to give FIFO underrun/overrun error every 3rd time
for mmc rescan command.
In current code FIFO_DEPTH is getting calculated after reading the default FIFOTH
register and extracting the RX_WMARK bits from it i.e (RX_WMARK = FIFO_DEPTH/2 -1).
Instead of storing the correct value, we were recalculating the FIFO_DEPT each
time which is not correct.Based on "[PATCH V9 3/9] DWMMC: Initialise dwmci and resolve EMMC read write issues"
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/160247Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
Acked-by: Simon Glass
Tested-by: Simon Glass
Acked-by: Jaehoon Chung
Acked-by: Andy Fleming
Signed-off-by: Minkyu Kang
15 Jun, 2013
1 commit
14 Jun, 2013
5 commits
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Enhance the MMC core to calculate the size of each MMC partition, and
update mmc->capacity whenever a partition is selected. This causes:mmc dev 0 1 ; mmcinfo
... to report the size of the currently selected partition, rather than
always reporting the size of the user partition.Signed-off-by: Stephen Warren
Signed-off-by: Andy Fleming -
After waiting for the command completion event, the interrupt status
bits, that occured to be set by that time, are cleared by writing them
back. It is supposed, that it should be command related bits (command
complete and may be command errors).However, in some cases the DMA already completes by that time before
the full transaction completes. The corresponding DINT bit gets set
and then cleared before even entering the loop, waiting for data part
completion. That waiting loop never gets this bit set, causing the
operation to hang. This is reported to happen, for example, for write
operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II
8GB card.The solution could be to explicitly clear only command related interrupt
status bits. However, since subsequent processing does not rely on
any command bits state, it could be easier just to remove clearing
of any bits at that point, leaving them all until all data processing
completes. After that the whole register will be cleared at once.Also, on occasion, interrupts masking moved to before writing the command,
just for the case there should be no chance of interrupt between the first
command and interrupts masking.Reported-by: Dirk Behme
Signed-off-by: Andrew Gabbasov
Acked-by: Dirk Behme
Signed-off-by: Andy Fleming -
Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode)
we see mx6 systems to hang after doing a 'save' command.Revert this commit since the original 'ifdef' logic from 7b43db92
(drivers/mmc/fsl_esdhc.c: fix compiler warnings) was the correct one.Reported-by: Tapani Utriainen
Signed-off-by: Fabio Estevam
Signed-off-by: Andy Fleming -
This patch fixes a bug related to mmc writes.
When doing fatwrites on an SD-Card, MMC bus problems can occur. Depending
on the size of the file, "MMC0: Bus busy timeout!" is reported, resulting
in an SD-Card that is no longer responding.
It appears to be, that set_cluster can be called with a size being zero.
That can be with a file that has a size being an exact multiple
(including 0) of the clustersize, but also for files that are smaller than
the size of one cluster.
The same problem occurs if the "mmc write" command is given with a block
count being 0.By adding a check for the block count being zero in mmc_write_blocks
(drivers/mmc.c), this problem is solved.Signed-off-by: Ruud Commandeur
Cc: Tom Rini
Cc: Benoît Thébaudeau
Cc: Mats Karrman
Cc: Andy Fleming
Signed-off-by: Andy Fleming -
CAP register don't have any information for 8-bit buswidth support
on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information.Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using
mmc_set_bus_width even if controller doesn't support.
Below change has code information.
"mmc: Properly determine maximum supported bus width"
(sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac)Bug log: mmcinfo
Error detected in status(0x208100)!
Device: zynq_sdhci
Manufacturer ID: fe
.....So enable 8-bit support only for 3.0 spec using CAP and for below 3.0
assign mmc->host_caps = MMC_MODE_8BIT on respective platform driver
if host have a support.Signed-off-by: Jagannadha Sutradharudu Teki
Signed-off-by: Andy Fleming
13 Jun, 2013
3 commits
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This patch adds APIs to access(open / close) and to resize boot partiton of EMMC.
Signed-off-by: Amar
Signed-off-by: Minkyu Kang -
This patch adds FDT support for DWMMC, by reading the DWMMC node data
from the device tree and initialising DWMMC channels as per data
obtained from the node.Signed-off-by: Vivek Gautam
Signed-off-by: Amar
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
This patch enumerates dwmci and set auto stop command during
dwmci initialisation.
EMMC read/write is not happening in current implementation
due to improper fifo size computation. Hence modified the fifo size
computation to resolve EMMC read write issues.Signed-off-by: Amar
Acked-by: Jaehoon Chung
Signed-off-by: Minkyu Kang
10 Jun, 2013
1 commit
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Update pbias programming sequence for OMAP5 ES2.0/DRA7
Signed-off-by: Balaji T K
Signed-off-by: Lokesh Vutla
30 May, 2013
1 commit
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Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
16 May, 2013
2 commits
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The logic for the whether to configure for polling or DMA
was mistakenly reversed in this patch:Commit 7b43db92110ec2f15c5f7187a165f2928464966b
drivers/mmc/fsl_esdhc.c: fix compiler warningsSigned-off-by: Haijun Zhang
CC: Sun Yusong-R58495
Signed-off-by: Andy Fleming -
Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement this new version of driver which is
10+ times faster than the old one.It's carefully designed to be compatible with Andes chips,
so it should be safe to replace it.Signed-off-by: Kuo-Jung Su
CC: Andy Fleming
Signed-off-by: Andy Fleming
15 May, 2013
1 commit
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The mpc85xx repuires a special layout on the memory device that is
connected to the eSDHC controller interface. But the file spl_mmc.c
didn't handle this specfic case, there needs a special treatmen, in
the powerpc drictory. So, there is no longer to keep spl_mmc.c on
mpc85xx, CONFIG_SPL_FRAMEWORK is not set.When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not
set, there was an error in drivers/mmc/spl_mmc.c:drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'.
Now, the solution is to move the file "spl_mmc.c" to directory "common/spl".
Signed-off-by: Ying Zhang
12 May, 2013
3 commits
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add mmc card support with atmel mci driver
Signed-off-by: Bo Shen
Signed-off-by: Andreas Bießmann -
Using IP version for different setting
- Higher version supports 8bit mode
- Higher version bus width setting is differentSigned-off-by: Bo Shen
Signed-off-by: Andreas Bießmann
11 May, 2013
2 commits
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Conflicts:
drivers/mtd/nand/mxc_nand_spl.c
include/configs/m28evk.h
10 May, 2013
2 commits
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Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo
function.Signed-off-by: Nishanth Menon
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TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs
Rename twl6035 to palmas to allow reuse across multiple current and
future platformsAs part of this change, change the CONFIG_TWL6035_POWER to
CONFIG_PALMAS_POWER and update usage of header file accordingly.Signed-off-by: Nishanth Menon
07 May, 2013
5 commits
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A malloc() followed by memset() can be simply replaced by calloc().
Signed-off-by: Fabio Estevam
Signed-off-by: Andy Fleming -
If failed the add_host(), it is reasonable that return value of
add_sdhci().Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
Signed-off-by: Andy Fleming -
Signed-off-by: Vipin Kumar
Acked-by: Stefan Roese
Acked-by: Jaehoon Chung
Signed-off-by: Andy Fleming -
Without this additional delay, some eMMC don't negotiate properly bus width
Tested on:
- Toshiba THGBM2G8D8FBAIB
- Toshiba THGBM4G4D1HBAR
- Micron MTFC4GMVEA (the one giving the problem)
- Hynix H26M64002BNR
- SanDisk SDIN5E1-32GSigned-off-by: Davide Bonfanti
Acked-by: Tom Rini
Signed-off-by: Andy Fleming -
Most of time that MMC driver spends on initializing a device is polling
OCR (operation conditions register). To decouple this polling loop,
device init is split into two parts: The first part fires the OCR query
command, and the second part polls the result. So the caller is now no
longer bound to the OCR-polling delay; he may fire the query, go
somewhere and then come back later for the result.To use this, call mmc_set_preinit() on any device which needs this.
This can save significant amounts of time on boot (e.g. 200ms) by
hiding the MMC init time behind other init.Signed-off-by: Che-Liang Chiou
Signed-off-by: Simon Glass
Acked-by: Jaehoon Chung
Signed-off-by: Andy Fleming
