13 Jan, 2021
1 commit
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Add COMMON_ENV(kernel_addr_r, fdt_addr_r and so on)
to fix a bug that faild to boot to ubuntu, failed
log as follows,
## Executing script at 80000000
load - load binary file from a filesystemUsage:
load [ [ [ [bytes [pos]]]]]
- Load binary file filename from partition part on device
type interface instance dev to address addr in memory.
bytes gives the size to load in bytes.
If bytes is 0 or omitted, the file is read until the end.
pos gives the file byte position to start reading from.
If pos is 0 or omitted, the file is read from the start.
...
Bad Linux ARM64 Image magic!
SCRIPT FAILED: continuing...Signed-off-by: Biwen Li
09 Nov, 2020
2 commits
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Update kernel_size_sd variable with correct value for lx2160a.
Signed-off-by: Manish Tomar
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Update kernelheader_addr and kernelheader_addr variables with correct values
for ls1043a.Signed-off-by: Manish Tomar
05 Nov, 2020
2 commits
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Starting with commit 7d9701db4089 ("cmd: mdio/mii: add Kconfig help and
allow break dependency"), CMD_MDIO depends on the PHYLIB Kconfig which
should be enabled properly from the Kconfig and not through any define
from a header file.Move all LS1088AQDS configs to enable PHYLIB and related through
Kconfig options. Also, remove the defines from the header file so that
we do not redefine the same symbol.Signed-off-by: Ioana Ciornei
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Starting with commit 7d9701db4089 ("cmd: mdio/mii: add Kconfig help and
allow break dependency"), CMD_MDIO depends on the PHYLIB Kconfig which
should be enabled properly from the Kconfig and not through any define
from a header file.Move all LS1088ARDB configs to enable PHYLIB and related through
Kconfig options. Also, remove the defines from the header file so that
we do not redefine the same symbol.Signed-off-by: Ioana Ciornei
29 Oct, 2020
9 commits
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This adds default environment variable for ls1012aqds
Signed-off-by: Biwen Li
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Add support of distro boot for ls1046aqds
Signed-off-by: Biwen Li
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Drop useless environment variable installer and qspi_bootcmd
for ls1012afrwy.
Only 2 MB nor flash in ls1012afrwy. So cannot get kernel(30 MB) from
the nor flash, then drop it.Signed-off-by: Biwen Li
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Enable CONFIG_MPC8XXX_GPIO for SoC LX2160A
Signed-off-by: Biwen Li
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Enable CONFIG_MPC8XXX_GPIO for LS208xA
Signed-off-by: Biwen Li
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Enable CONFIG_MPC8XXX_GPIO for LS1088A
Signed-off-by: Biwen Li
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Enable CONFIG_MPC8XXX_GPIO for SoC LS1028A
Signed-off-by: Biwen Li
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Enable CONFIG_MPC8XXX_GPIO for SoC LS1043A
Signed-off-by: Biwen Li
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Enable CONFIG_MPC8XXX_GPIO for SoC LS1012A
Signed-off-by: Biwen Li
19 Oct, 2020
1 commit
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mux changes in board file to enable lpuart1 and macro
define for lpuart1 used for mux changes in board configuation
register 13Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang
29 Sep, 2020
4 commits
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Add the environment 'vscfw_addr' to assign a default address for
vsc7385 firmware uploading.Signed-off-by: Hou Zhiqiang
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Add compatible string "gianfar" support and update the
device-tree-bindings doc.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled
for P1010RDB board.Signed-off-by: Hou Zhiqiang
Reviewed-by: Priyanka Jain
18 Sep, 2020
1 commit
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This reverts commit d959fbe5d74506447f4a9ea9feda1b02e1889179.
The workaround of A-011451 of LX2160A rev1 PCIe results in i.MX
boot crash in Linux factory uboot tree. And the LX2160A rev1
won't supported anymore in LSDK release. So, revert the WA patch.Signed-off-by: Hou Zhiqiang
08 Sep, 2020
2 commits
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This patch add base support for LX2162AQDS board.
LX2162AQDS board supports LX2162A family SoCs.
This patch add basic support of platform.Signed-off-by: Ioana Ciornei
Signed-off-by: Zhao Qiang
Signed-off-by: hui.song
Signed-off-by: Manish Tomar
Signed-off-by: Vikas Singh
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Priyanka Jain -
Update "sd_bootcmd" env variable to select mmc device via
"mmc dev" command before accessing.Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Priyanka Jain
27 Aug, 2020
8 commits
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The process for eMMC HS400 mode for eSDHC is,
1. Perform the Tuning Process at the HS400 target operating frequency.
Latched the clock division value.
2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG].
3. Switch to High Speed mode and then set the card clock frequency to
a value not greater than 52Mhz
4. Clear TBCTL[TB_EN],tuning block enable bit.
5. Change to 8 bit DDR Mode
6. Switch the card to HS400 mode.
7. Set TBCTL[TB_EN], tuning block enable bit.
8. Clear SYSCTL[SDCLKEN]
9. Wait for PRSSTAT[SDSTB] to be set
10. Change the clock division to latched value.Set TBCTL[HS 400 mode]
and Set SDCLKCTL[CMD_CLK_CTRL]
11. Set SYSCTL[SDCLKEN]
12. Wait for PRSSTAT[SDSTB] to be set
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
14. Wait for delay chain to lock.
15. Set TBCTL[HS400_WNDW_ADJUST]
16. Again clear SYSCTL[SDCLKEN]
17. Wait for PRSSTAT[SDSTB] to be set
18. Set ESDHCCTL[FAF]
19. Wait for ESDHCCTL[FAF] to be cleared
20. Set SYSCTL[SDCLKEN]
21. Wait for PRSSTAT[SDSTB] to be set.Signed-off-by: Yangbo Lu
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Add a mmc_hs400_prepare_ddr() interface for controllers
which needs preparation before switching to DDR mode for
HS400 mode.Signed-off-by: Yangbo Lu
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Add a hs400_tuning flag to identify the tuning for HS400 mode.
Signed-off-by: Yangbo Lu
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Support tuning process for eMMC HS200 for eSDHC.
Signed-off-by: Yangbo Lu
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For DM_MMC, the controller re-initialization is needed to
clear old configuration for mmc rescan.Signed-off-by: Yangbo Lu
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The eSDHC adapter card identification and multiplexing configuration
through FPGA had been implemented in both common mmc driver and
fsl_esdhc driver. However it is proper to move these code to board
files and do it during board initialization. The FPGA registers are
also board specific.This patch is to move eSDHC adapter card identification and
multiplexing configuration from mmc driver to specific board files.
And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed.Signed-off-by: Yangbo Lu
[Rebased, Removed T1040QDS change as board does not exist]
Signed-off-by: Priyanka Jain -
When eSDHC operates at 3.3v, damage can accumulate in an internal
level shifter at a higher than expected rate. The faster the interface
runs, the more damage accumulates. This issue now is found on LX2160A
eSDHC1 for only SD card.The hardware workaround is recommended to use an on-board level shifter
that is 1.8v on SoC side and 3.3v on SD card side.For boards without hardware workaround, this option could be enabled,
ensuring 1.8v IO voltage and disabling eSDHC if no card.
This option assumes no hotplug, and u-boot has to make all the way to
to linux to use 1.8v UHS-I speed mode if has card.
If you do not want the workaround for better user experience, of course
you can choose to not select it running eSDHC in unsafe mode.Signed-off-by: Yangbo Lu
Acked-by: Peng Fan -
Add a few defines related to ARI and SRIOV configuration.
Signed-off-by: Laurentiu Tudor
10 Jul, 2020
3 commits
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CONFIG_ENV_OVERWRITE disable write protection on various environment
variables like "ethaddr" and "serial".Define the config in LS1046A and LS1012A common header as both of them
require this entry. Also, resolve an error while setting multiple values
of "ethaddr" variable.Before the change:
=> setenv ethaddr 00:E0:0C:00:06:0
=> setenv ethaddr 00:E0:0C:00:06:1
Error: Can't overwrite "ethaddr"
Error inserting "ethaddr" variable, errno=1After the change:
=> setenv ethaddr 00:E0:0C:00:06:0
=> setenv ethaddr 00:E0:0C:00:06:1Signed-off-by: Kuldeep Singh
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Currently PFE firmware access only 64K from flash and has designated
space of 3M in LSDK memory layout. Increase the config value and read
entire PFE firmware.Signed-off-by: Kuldeep Singh
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Previous attempt to increase CONFIG_SYS_MALLOC_LEN was done in commit
c084a8edf4e2 ("configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size")
which increased malloc memory to ~1M.PFE firmware alone requires 3M of dynamic memory allocation and
therefore, increase the config value to a larger value i.e 5M. This size
should be enough as of now to accommodate further memory requirements.Signed-off-by: Kuldeep Singh
22 Jun, 2020
1 commit
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Add xspi boot source to qixis command to let the soc boot from
flex-nor flash chip.Signed-off-by: Yuantian Tang
09 Jun, 2020
1 commit
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This enables SYS_I2C_MXC to fix a bug that
failed to boot from sd card with
image u-boot-with-spl-pbl.binSigned-off-by: Biwen Li
03 Jun, 2020
3 commits
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The test pings the local IP address though different ports of a sandbox
DSA device. Port traffic is filtered and the test verifies that ping
works only on enabled ports.
The additional interfaces require MAC addresses, these have been added
to sandbox default environment.Signed-off-by: Alex Marginean
Signed-off-by: Claudiu Manoil -
DSA stands for Distributed Switch Architecture and it covers switches that
are connected to the CPU through an Ethernet link and generally use frame
tags to pass information about the source/destination ports to/from CPU.
Front panel ports are presented as regular ethernet devices in U-Boot and
they are expected to support the typical networking commands.
DSA switches may be cascaded, DSA class code does not currently support
this.Signed-off-by: Alex Marginean
Signed-off-by: Vladimir Oltean
Signed-off-by: Claudiu Manoil -
LS1088A-RDB has MMC, SCSI, DHCP as boot targets,
but the USB support was missing.
Add support for USB as BOOT_TARGET_DEVICES.Signed-off-by: Era Tiwari
Signed-off-by: Pramod Kumar
15 May, 2020
1 commit
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When LAYERSCAPE Gen4 PCIe controller is sending multiple split
completions and ACK latency expires indicating that ACK should
be send at priority. But because of large number of split
completions and FC update DLLP, the controller does not give
priority to ACK transmission. This results into ACK latency
timer timeout error at the link partner and the pending TLPs
are replayed by the link partner again.Workaround:
1. Reduce the ACK latency timeout value to a very small value.
2. Restrict the number of completions from the PCIe controller
to 1, by changing the Max Read Request Size (MRRS) of link
partner to the same value as Max Packet size (MPS).This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.
Signed-off-by: Hou Zhiqiang
08 May, 2020
1 commit
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CONFIG_SYS_MALLOC_LEN is currently set to low value and leaves very less
space to do malloc in flash environmet. Increase the value to get more
memory and also make it align with other boards(ls1046a, ls1043a etc.)
config values.Signed-off-by: Kuldeep Singh