10 Apr, 2020
1 commit
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This reverts commit 2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee.
The commit breaks uboot boot (hang in ddr init)
on many PowerPC boards like P3041DS, P4080DSSigned-off-by: Biwen Li
Signed-off-by: Priyanka Jain
23 Dec, 2019
1 commit
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Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.Signed-off-by: Joakim Tjernlund
Signed-off-by: Priyanka Jain
26 Aug, 2019
1 commit
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add DM_I2C support for this driver.
Signed-off-by: Heiko Schocher
Reviewed-by: Prabhakar Kushwaha
22 Aug, 2019
1 commit
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DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch solves
the problem that the i2c-related api of the lx2160a platform does not
support dm.Signed-off-by: Chuanhua Han
Reviewed-by: Prabhakar Kushwaha
12 Aug, 2019
1 commit
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Move this function over to the new header file.
Signed-off-by: Simon Glass
Acked-by: Joe Hershberger
21 May, 2019
1 commit
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CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.Signed-off-by: Mario Six
03 Mar, 2019
1 commit
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Moves below DDR specific defines to Kconfig:
CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESHSigned-off-by: Rajesh Bhagat
Reviewed-by: York Sun
Reviewed-by: Prabhakar Kushwaha
19 Feb, 2019
1 commit
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fsl_ddr_board_options is generally defined in board
board's ddr.c, but some boards like lx2160ardb board
does not need this function.
Defining fsl_ddr_board_options as weak function to
resolve compilation errors for such boards.Signed-off-by: Priyanka Jain
[PK: Fix checkpatch warnings]
Signed-off-by: Prabhakar Kushwaha
07 Dec, 2018
1 commit
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LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUsSigned-off-by: Bao Xiaowei
Signed-off-by: Hou Zhiqiang
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Vabhav Sharma
Signed-off-by: Sriram Dash
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun
27 Jul, 2018
1 commit
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Pass an empty buffer instead of NULL if the hwconfig environment
variable isn't set.Signed-off-by: Jeremy Gebben
Cc: Stefano Babic
Cc: York Sun
Reviewed-by: York Sun
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
28 Apr, 2018
1 commit
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We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.Signed-off-by: Tom Rini
15 Feb, 2018
1 commit
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Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4.Signed-off-by: Tom Rini
10 Feb, 2018
1 commit
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To make this driver easier to be reused, dual-license DDR driver.
Signed-off-by: York Sun
CC: Simon Glass
CC: Tom Rini
CC: Heinrich Schuchardt
CC: Thomas Schaefer
CC: Masahiro Yamada
CC: Robert P. J. Day
CC: Alexander Merkle
CC: Joakim Tjernlund
CC: Curt Brune
CC: Valentin Longchamp
CC: Wolfgang Denk
CC: Anatolij Gustschin
CC: Ira W. Snyder
CC: Marek Vasut
CC: Kyle Moffett
CC: Sebastien Carlier
CC: Stefan Roese
CC: Peter Tyser
CC: Paul Gortmaker
CC: Peter Tyser
CC: Jean-Christophe PLAGNIOL-VILLARD
31 Jan, 2018
6 commits
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Variable "row_density" is no longer used. Drop it from DIMM structure.
Signed-off-by: York Sun
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DDR controllers always use binding register to determine the memory
space to perform data initialization. In case of controller interleaving,
the space is doubled, resulting twice long wait. It wasn't too bad until
the memory capacity increases. To reduce the wait time, reduce the
binding space to half and restore it after data initialization.
Three-way interleaving is no longer used and is removed.Signed-off-by: York Sun
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DDR4 RDIMM has some information in SPD to be used to calculate the
control words for register chip. The rest can be found from JEDEC
spec DDR4RCD02.Signed-off-by: York Sun
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On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.Signed-off-by: York Sun
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Wrong field was masked in this workaround due to wrong endianness. The
impacted SoCs have big-endian.Signed-off-by: York Sun
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For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.Signed-off-by: York Sun
24 Jan, 2018
1 commit
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Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCsSigned-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
Reviewed-by: York Sun
11 Sep, 2017
1 commit
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LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.Signed-off-by: Alison Wang
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Signed-off-by: Raghav Dogra
Signed-off-by: Shaohui Xie
[YS: Revised commit message]
Reviewed-by: York Sun
16 Aug, 2017
1 commit
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We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.Suggested-by: Wolfgang Denk
Signed-off-by: Simon Glass
13 Jun, 2017
1 commit
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Fix compiling error of "no member named 'taamin_ps'" for DDR2.
Signed-off-by: York Sun
06 Jun, 2017
2 commits
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We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.Signed-off-by: Simon Glass
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The declarations should not be in common.h. Move them to the arch-specific
headers.Signed-off-by: Simon Glass
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini
18 Apr, 2017
3 commits
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(pdimm[0].data_width >= 32) || (pdimm[0].data_width
Reviewed-by: Tom Rini
Reviewed-by: York Sun -
Depending on DDR configuration, gcc-6.x will show up unused-const-
variable messages. Use __maybe_unused specifier for all dynamic_odt
variable definitions to remove these warnings.Memory footprint will not increase as gcc will optimize out unused
constants.Signed-off-by: Thomas Schaefer
Signed-off-by: York Sun
13 Apr, 2017
1 commit
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This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.Signed-off-by: Simon Glass
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini
06 Apr, 2017
1 commit
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At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese
05 Jan, 2017
5 commits
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These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.Signed-off-by: York Sun
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Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.Signed-off-by: York Sun
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Use Kconfig to select errata workaround.
Signed-off-by: York Sun
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Use Kconfig to select errata workaround.
Signed-off-by: York Sun
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Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.Signed-off-by: York Sun
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini
06 Dec, 2016
2 commits
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- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.Signed-off-by: Shengzhou Liu
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun -
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
24 Nov, 2016
2 commits
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Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.Signed-off-by: York Sun
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Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing
macros.Signed-off-by: York Sun