07 May, 2020
1 commit
-
Current MDIO wait time is too long, which introduce long delay when
PHY negotiation register checking. Reduce it to 10usSigned-off-by: Ye Li
Reviewed-by: Fugang Duan
27 Apr, 2020
10 commits
-
Reset PHY once is enough that can reduce the time cost
to get IP after the first time.Reviewed-by: Frank Li
Signed-off-by: Fugang Duan
(cherry picked from commit 2342d9670a6e349a462e24febdc085aac3bedcee) -
Update dwc qos driver for i.MX8DXL
Signed-off-by: Fugang Duan
(cherry picked from commit d1e718565972495c99345ee8119651ffa14a3238) -
Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.Signed-off-by: Ye Li
Reviewed-by: Fugang Duan
(cherry picked from commit d00d6d0a22ba734f76444621a17f985ffba50705) -
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.Signed-off-by: Ye Li
Reviewed-by: Fugang Duan
(cherry picked from commit e442274ddd2cb6e9c4103e91cd284bfb01a4a636) -
Implement the callbacks to get phy mode interface and txclk
rate configuration.Reviewed-by: Ye Li
Signed-off-by: Fugang Duan
(cherry picked from commit ad2f34236694493b94c2cf6801eef4b7212eb89b) -
Add dwc eqos for imx support.
Reviewed-by: Ye Li
Signed-off-by: Fugang Duan
(cherry picked from commit 52751a41c92a719891c8154cfc488165cc42f713) -
Add RX delay enable support for RTL8211F PHY.
Reviewed-by: Ye Li
Signed-off-by: Fugang Duan
(cherry picked from commit 8e55d1e0bea57c0671a51258c48306be0066ae7c) -
Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
(cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db)
(cherry picked from commit 99b54a6965904a879afdb6883a519de726cb4e96) -
Update eQoS and fec ethernet drivers to support shared MDIO framework
Signed-off-by: Ye Li
(cherry picked from commit 5ce41af29fad17b2d26a96e589716ae5b617355e) -
For dual ethernet controllers, the HW design may connect ETH phys to
one MDIO ports. So two different ethernet drivers have to share MDIO bus.
Since two ethernet drivers are independent, we can't ensure their probe order.To resolve this problem, introduce an eth phy generic driver and uclass.
After eth-uclass binds, we search the mdio node and binds the phy node with
the eth-phy-generic driver.When one eth driver get its phy device, the parent of phy device will probe prior than
phy device. So this ensure the eth driver ownes the MDIO bus will be probed
before using its MDIO.Signed-off-by: Ye Li
23 Apr, 2020
2 commits
-
Add support for more clocks used by iMX8 from DTB:
ref_clock, tx_2x_clock, ahb_clock
And update get clock rate interface to support multiple fec ports.Signed-off-by: Ye Li
-
When the power domain driver is enabled, we need to enable clocks after power
domain on. So the clock settings can't set in board_init, needs to set them
when the device is probed. Add this weak function in driver, that SoC codes
can implement the clock settings.Reviewed-by: Peng Fan
Signed-off-by: Ye Li
(cherry picked from commit c0e4ac66196b20f363f711fb18e40b70e3be9240)
(cherry picked from commit 187ea376980be12e69c45bd6e62c7ca1559046f6)
(cherry picked from commit 9c0be2929558498429b31868d67e1d6695546ac9)
04 Apr, 2020
1 commit
-
To access the PHY, the MAC registers must be initialized. Call the init
function in probe() to make it so, otherwise the PHY ID readout returns
all zeroes.Signed-off-by: Marek Vasut
Cc: Joe Hershberger
Cc: Nobuhiro Iwamatsu
31 Mar, 2020
1 commit
-
When MACB_ZYNQ is enabled there is compilation warnings
drivers/net/macb.c: In function ‘_macb_init’:
drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function);
did you mean ‘MACB_MCF’?
writel((value), (port)->regs + MACB_##reg)
^~~~~It has been caused by changing macros name by commit below.
Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux")
Signed-off-by: Michal Simek
Acked-by: Joe Hershberger
30 Mar, 2020
3 commits
-
The correct setting for the RGMII ports on LS1046ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.Fixes: cc1aa218f510 ("armv8/ls1046a: RGMII PHY requires internal
delay on Tx")
Signed-off-by: Madalin Bucur
Reviewed-by: Priyanka Jain -
The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.Fixes: 5a78a472f666 ("armv8/ls1043a: RGMII PHY requires internal
delay on Tx")
Signed-off-by: Madalin Bucur
Reviewed-by: Priyanka Jain -
The RGMII modes that include internal delay were not all
properly treated in the memac code. Add support for all
RGMII delay modes.Fixes: 111fd19e3b9e ("fm/mEMAC: add mEMAC frame work")
Signed-off-by: Madalin Bucur
Reviewed-by: Priyanka Jain
10 Mar, 2020
7 commits
-
The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.The uid and mask bits 3:0 are now again the same as in the Linux kernel.
Signed-off-by: Clemens Gruber
-
This patch adds ability to switch beetween two PHY SGMII modes.
Some hardware, for example, FPGA IP designs may use 6-wire mode
which enables differential SGMII clock to MAC.Patch description, dt flags have been done in mainline Linux by
commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")Signed-off-by: Michal Simek
Acked-by: Joe Hershberger -
Commit 27c3f70f3b50 ("net: phy: Increase link up delay in
genphy_update_link()") increased the per-iteration waiting time from
1ms to 50ms, without adjusting the timeout counter. This lead to the
timeout increasing from the typical 4 seconds to over three minutes.Adjust the timeout counter evaluation by that factor of 50 to bring the
timeout back to the intended value.Signed-off-by: Andre Przywara
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Reviewed-by: Stefan Roese
Tested-by: Matthias Brugger
Tested-by: Simon Goldschmidt
Acked-by: Joe Hershberger -
The driver now unconditionally prints some information that's not
universally useful. Replace printf with debug.Signed-off-by: Alex Marginean
Reviewed-by: Priyanka Jain
Acked-by: Joe Hershberger -
Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid
protocol configuration. The PHY doesn't support it, it's just used as an
alias for one of the other two protocols.Signed-off-by: Florin Chiculita
Signed-off-by: Alex Marginean
Reviewed-by: Priyanka Jain
Acked-by: Joe Hershberger -
Add NC-SI to the usual phy handling. This makes two notable changes:
- Somewhat similar to a fixed phy, phy_connect() will create an NC-SI
phy if CONFIG_PHY_NCSI is defined.
- An early return is added to phy_read() and phy_write() to handle a
case like the NC-SI phy which does not define a bus.Signed-off-by: Samuel Mendoza-Jonas
Reviewed-by: Joel Stanley
Acked-by: Joe Hershberger -
This introduces support for the NC-SI protocol, modelled as a phy driver
for other ethernet drivers to consume.NC-SI (Network Controller Sideband Interface) is a protocol to manage a
sideband connection to a proper network interface, for example a BMC
(Baseboard Management Controller) sharing the NIC of the host system.
Probing and configuration occurs by communicating with the "remote" NIC
via NC-SI control frames (Ethernet header 0x88f8).This implementation is roughly based on the upstream Linux
implementation[0], with a reduced feature set and an emphasis on getting
a link up as fast as possible rather than probing the full possible
topology of the bus.
The current phy model relies on the network being "up", sending NC-SI
command frames via net_send_packet() and receiving them from the
net_loop() loop (added in a following patch).The ncsi-pkt.h header[1] is copied from the Linux kernel for consistent
field definitions.[0]: https://github.com/torvalds/linux/tree/master/net/ncsi
[1]: https://github.com/torvalds/linux/blob/master/net/ncsi/ncsi-pkt.hSigned-off-by: Samuel Mendoza-Jonas
Reviewed-by: Joel Stanley
Acked-by: Joe Hershberger
28 Feb, 2020
3 commits
-
Driver probe function is called again and again in case of error.
Malloc space is getting full which is is reported by:
Insufficient RAM for page table: 0x15000 > 0x14000.
Please increase the size in get_page_table_size()
### ERROR ### Please RESET the board ###The patch is freeing allocated buffers on error path to avoid panic.
Signed-off-by: Michal Simek
-
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.
Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek
Reviewed-by: Grygorii Strashko -
flush_dcache_range() expects unsigned long in the arguments. Here u32
variable is unable to hold the higher address value when ddr mapped
to higher addresses & flushing lower address dchache range instead
which is unmapped causing to crash.Signed-off-by: T Karthik Reddy
Signed-off-by: Michal Simek
19 Feb, 2020
2 commits
-
The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.Factor them out to , and make all drivers to
include instead of .If we need to differentiate them for some architectures, we can
move the generic definitions to .Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.Signed-off-by: Masahiro Yamada
-
dma_unmap_single() takes the dma address, not virtual address.
Signed-off-by: Masahiro Yamada
11 Feb, 2020
1 commit
-
sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
08 Feb, 2020
3 commits
-
building mtk ethernet driver for aarch64 (mt7622) results
in warnings/errors"error: cast from pointer to integer of different size"
Fixes: 23f17164d9 ("ethernet: MediaTek: add ethernet driver for MediaTek ARM-based SoCs")
Signed-off-by: Frank Wunderlich -
This patch add mt7622 support in mediatek eth driver
Signed-off-by: MarkLee
-
This patch add sgmii init part for the mediatek SoC that
support sgmii mode. It is a must for mt7622.Signed-off-by: MarkLee
06 Feb, 2020
2 commits
-
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
-
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin
05 Feb, 2020
1 commit
-
- DFU support file operations lager then the default max size
- add dfu support to dwc2 for bcm2835
- enable DFU for RPi4
- Fix RPi4 memory map to include the genet device
- add driver for the genet ethernet device
- enable network support in RPi4 config
31 Jan, 2020
1 commit
-
Signed-off-by: Flavio Suligoi
30 Jan, 2020
1 commit
-
The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs
and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4.
There is no publicly available documentation, so this driver is based
on the Linux driver. Compared to that the queue management is
drastically simplified, also we only support version 5 of the IP and
RGMII connections between MAC and PHY, as used on the RPi4.Signed-off-by: Amit Singh Tomar
Reviewed-by: Andre Przywara
[Andre: heavy cleanup and a few fixes]
Signed-off-by: Andre Przywara
Tested-by: Corentin Labbe
Signed-off-by: Matthias Brugger
26 Jan, 2020
1 commit
-
Updates and fixes for ls1028a, lx2160a, ls1012a, ls1021a, ls2080a,
ls1088a platforms:
- lx2-rev2 pcie support, enetc related updates, layerscape-pcie fixes