23 Oct, 2012

6 commits

  • The P5040 does not have SRIO, so don't put the SRIO definitions in
    corenet_ds.h. They belong in the board-specific header files.

    Signed-off-by: Timur Tabi
    Signed-off-by: Andy Fleming

    Timur Tabi
     
  • The P5040 does not have SRIO support, so there are no SRIO LIODNs.
    Therefore, the functions that set the SRIO LIODNs should not be compiled.

    Signed-off-by: Timur Tabi
    Signed-off-by: Andy Fleming

    Timur Tabi
     
  • The liodn for the new PCIE controller included in P5040DS is no longer set
    through a register in the guts register block but with one in the PCIE
    register block itself. Update the PCIE CCSR structure to add the new liodn
    register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
    the liodn in the correct register.

    Signed-off-by: Laurentiu Tudor
    Signed-off-by: Timur Tabi
    Signed-off-by: Andy Fleming

    Laurentiu Tudor
     
  • Commit 709389b6 unintentionally used the Unicode version of the
    apostrophy. Replace it with the normal ASCII version.

    Signed-off-by: Timur Tabi
    Signed-off-by: Andy Fleming

    Timur Tabi
     
  • Erratum: A-004034
    Affects: SRIO

    Description: During port initialization, the SRIO port performs
    lane synchronization (detecting valid symbols on a lane) and
    lane alignment (coordinating multiple lanes to receive valid data
    across lanes). Internal errors in lane synchronization and lane
    alignment may cause failure to achieve link initialization at
    the configured port width.

    An SRIO port configured as a 4x port may see one of these scenarios:

    1. One or more lanes fails to achieve lane synchronization.
    Depending on which lanes fail, this may result in downtraining
    from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).

    2. The link may fail to achieve lane alignment as a 4x, even
    though all 4 lanes achieve lane synchronization, and downtrain
    to a 1x. An SRIO port configured as a 1x port may fail to complete
    port initialization (PnESCSR[PU] never deasserts) because of
    scenario 1.

    Impact: SRIO port may downtrain to 1x, or may fail to complete
    link initialization. Once a port completes link initialization
    successfully, it will operate normally.

    Signed-off-by: Liu Gang
    Signed-off-by: Andy Fleming

    Liu Gang
     
  • Fix usb device-tree fixup:
    - wrong modification of dr_mode and phy_type when
    "usb1" is not mentioned inside hwconfig string;
    now allows hwconfig strings like:
    "usb2:dr_mode=host,phy_type=ulpi"
    - add warning message for using usb_dr_mode
    and usb_phy_type env variables (if either is used)

    Signed-off-by: Ramneek Mehresh
    Signed-off-by: Andy Fleming

    ramneek mehresh
     

22 Oct, 2012

5 commits

  • P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
    workaround conditional.
    In formal release document, the errata number should be ESDHC13 instead
    of ESDHC136.

    Signed-off-by: Roy Zang
    Signed-off-by: Andy Fleming

    Zang Roy-R61911
     
  • QIXIS FPGA layout defines the address of registers but The actual register bit
    implementation is board-specific,

    So avoid use of magic numbers as it may vary across different boards's QIXIS
    FPGA implementation.
    Also, Avoid board specific defines in common/qixis.h

    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Andy Fleming

    Prabhakar Kushwaha
     
  • We should only write TSR_WIS to the SPRN_TSR register in
    reset_85xx_watchdog.

    The old code would cause the timer interrupt to be acknowledged when the
    watchdog was reset, and we would then get no more timer interrupts.
    This bug would affect all mpc85xx boards that have the watchdog enabled.

    Signed-off-by: Mark Marshall
    Signed-off-by: Andy Fleming

    Mark Marshall
     
  • Users of familiar with the Linux gpiolib API expect that value parameter
    to gpio_direction_output reflects the initial state of the output pin.
    gpio_direction_output was always driving the output low, now it drives
    it high or low according to the value provided.

    Signed-off-by: Chris Packham
    Cc: Kyle Moffett
    Cc: Andy Fleming
    Cc: Peter Tyser
    Cc: Kumar Gala
    Signed-off-by: Andy Fleming

    Chris Packham
     
  • The original code uses 'Programming Interface' field to judge if PCIE is
    EP or RC mode, however, T4240 does not support this functionality.
    According to PCIE specification, 'Header Type' offset 0x0e is used to
    indicate header type, so for PCIE controller, the patch changes code to
    use 'Header Type' field to identify if the PCIE is EP or RC mode.

    Signed-off-by: Minghuan Lian
    Signed-off-by: Andy Fleming

    Minghuan Lian
     

20 Oct, 2012

24 commits


19 Oct, 2012

5 commits