09 Aug, 2019
1 commit
-
Add PCIE relevant clocks to clk-imx8 driver, so PCIE IMX driver can
set the clocks through DTBSigned-off-by: Ye Li
26 Jul, 2019
1 commit
-
Add the SATA clocks to clk-imx8, so we can use clk uclass interfaces
to access the clocks in AHCI driver.Signed-off-by: Ye Li
04 Jul, 2019
1 commit
-
Fix the issue that using imx8qxp ENET clock name in iMX8QM table.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
24 May, 2019
2 commits
-
Update imx8 clock driver to support LPCG and full clocks tree for some
modules aligned with kernel. And add the imx8qm clock tree.We divide the clock to serveral types: slice, fixed, lpcg, gpr, mux.
Generally slice and fixed clocks are the sources. lpcg, gpr and mux are
the downstream of those sources and are used for gating, muxing or dividing
functions.Notice: since the clock depends on the power domain of its resource, must power
on the resource firstly, then we can get clock. Otherwise, we can't access lpcg.
Thus, the clock dump only dumps the slice clock.Signed-off-by: Ye Li
-
The SCFW get clock rate API only return u32, but we use a ulong to
get the value. The ulong variable is not initialized, so on stack
it higher 32 bits may not zero, and return invalid rate.Signed-off-by: Ye Li
02 Apr, 2019
1 commit
-
CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.Signed-off-by: Jagan Teki
26 Mar, 2019
3 commits
-
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms.
This allows the MMCIF driver to set higher clock rate if desired.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
The $div and $mul values were swapped in the debug output,
fix this.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
09 Mar, 2019
3 commits
-
EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.Cc: Joe Hershberger
Signed-off-by: Jagan Teki
Acked-by: Joe Hershberger -
- Implement EMAC, GMAC clocks via ccu_clk_gate for
all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
supported Allwinner SoCs.Cc: Joe Hershberger
Signed-off-by: Jagan Teki
Acked-by: Joe Hershberger -
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.
Which would eventually used in sunxi_emac.c driver.
Signed-off-by: Jagan Teki
04 Mar, 2019
1 commit
-
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
Allwinner SoCs.Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara
01 Mar, 2019
1 commit
-
- Gen2/Gen3 fixes for warnings and sdhi
27 Feb, 2019
2 commits
-
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Simon Glass -
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.Based on code written by Wesley Terpstra
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linuxBoot and PLL rate change were tested on a SiFive HiFive Unleashed
board.Signed-off-by: Paul Walmsley
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
25 Feb, 2019
1 commit
-
Drop per SoC def_bool on each driver, since this is now implied by
SoC Kconfig option instead.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
09 Feb, 2019
6 commits
-
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.Signed-off-by: Patrick Delaunay
-
Add support of clk dump command and
display information during probe (under CONFIG_DISPLAY_CPUINFO).Signed-off-by: Patrick Delaunay
-
Because stgen is initialized with HSI clock, we need to
recalculate the counter when changing frequency.Signed-off-by: Lionel Debieve
Signed-off-by: Patrick Delaunay -
Remove unnecessary setbits on set/clear registers.
Avoid to deactivate HSI with HSE.Signed-off-by: Patrick Delaunay
-
Add support for enable/disable of IPCC clock using AHB3 registers
Signed-off-by: Patrick Delaunay
-
Remove support of ck_usbo_48m clock node in device tree,
but force 48MHz frequency to prepare alignment
with kernel device tree.Signed-off-by: Patrick Delaunay
01 Feb, 2019
3 commits
-
These clocks are needed to get MMC running. We don't actually support
setting them yet.Signed-off-by: Simon Glass
Reviewed-by: Philipp Tomsich -
It is helpful to print the clock number as well as the index, so that this
can be looked up in the binding file. Update the debug() statement to do
this.Signed-off-by: Simon Glass
Reviewed-by: Philipp Tomsich -
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.pySigned-off-by: Simon Glass
Reviewed-by: Philipp Tomsich
30 Jan, 2019
3 commits
-
Some Allwinner clock devices have parent clocks and reset gates itself,
which need to be activated for them to work.Add some code to just assert all resets and enable all clocks given.
This should enable the A80 MMC config clock, which requires both to be
activated. The full CCU devices typically don't require resets, and have
just fixed clocks as their parents. Since we treat both as optional and
enabling fixed clocks is a NOP, this works for all cases, without the need
to differentiate between those clock types.Signed-off-by: Andre Przywara
Acked-by: Jagan Teki -
The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.Signed-off-by: Andre Przywara
[jagan: fix a80 mmc clock config compatible]
Signed-off-by: Jagan Teki
Reviewed-by: Jagan Teki -
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.We don't advertise the mod clock yet, as this is still handled by the
MMC driver.Signed-off-by: Andre Przywara
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki
Reviewed-by: Jagan Teki
19 Jan, 2019
11 commits
-
Add initial clock driver for Allwinner A80.
- Implement UART bus clocks via ccu_clk_gate table for
A80, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.cSigned-off-by: Jagan Teki
-
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.cSigned-off-by: Jagan Teki
Reviewed-by: Andre Przywara -
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara -
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara -
Add initial clock driver for Allwinner V3S.
- Implement USB bus and USB clocks via ccu_clk_gate table
for V3S, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for V3S, so it can accessed in common reset deassert
and assert functions from reset-sunxi.cSigned-off-by: Jagan Teki
Acked-by: Maxime Ripard -
Add initial clock driver for Allwinner R40.
- Implement USB bus and USB clocks via ccu_clk_gate
for R40, so it can accessed in common clk enable
and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for R40, so it can accessed in common reset deassert
and assert functions from reset-sunxi.cSigned-off-by: Jagan Teki
Acked-by: Maxime Ripard -
Add initial clock driver for Allwinner A83T.
- Implement USB bus and USB clocks via ccu_clk_gate table
for A83T, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for A83T, so it can accessed in common reset deassert
and assert functions from reset-sunxi.cSigned-off-by: Jagan Teki
Acked-by: Maxime Ripard -
Add initial clock driver for Allwinner A23/A33.
- Implement USB bus and USB clocks via ccu_clk_gate table
for A23/A33, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for A23/A33, so it can accessed in common reset deassert
and assert functions from reset-sunxi.cSigned-off-by: Jagan Teki
Acked-by: Maxime Ripard -
Add initial clock driver for Allwinner A31.
- Implement USB ahb1 and USB clocks via ccu_clk_gate table
for A31, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table
for A31, so it can accessed in common reset deassert
and assert functions from reset-sunxi.cSigned-off-by: Jagan Teki
Acked-by: Maxime Ripard -
Add initial clock driver for Allwinner A10s/A13.
- Implement USB ahb and USB clocks via ccu_clk_gate table
for A10s/A13, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.cSigned-off-by: Jagan Teki
Acked-by: Maxime Ripard -
Add initial clock driver for Allwinner A10/A20.
- Implement USB ahb and USB clocks via ccu_clk_gate table
for A10/A20, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.cSigned-off-by: Jagan Teki
Acked-by: Maxime Ripard