04 Mar, 2019
1 commit
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With current order of include files, the file designware_spi.c
can't see that the struct global_data has the member
board_type when CONFIG_BOARD_TYPES is defined. By not seeing this
then all the members are shifted in the struct global_data.
So when the driver is trying to read from device tree blob, it
would pass the wrong address to the function 'fdtdev_get_int'.
This will make to use the default frequency 500000.The fix consists of changing the order of include files in
designware_spi.c to include first common.h file.Signed-off-by: Horatiu Vultur
Reviewed-by: Jagan Teki
19 Dec, 2018
1 commit
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On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.Signed-off-by: Gregory CLEMENT
03 Oct, 2018
1 commit
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Add code to reset all reset signals as in SPI DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.Release reset when _remove().
Signed-off-by: Ley Foon Tan
Acked-by: Marek Vasut
Reviewed-by: Jagan Teki
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
23 Apr, 2018
1 commit
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While switching to readl_poll_timeout macros from custom code
the waiting condition was accidently inverted, so it was pure
luck that this code works at least in some conditions.Fix that by inverting exit condition for readl_poll_timeout.
Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush")
Signed-off-by: Eugeniy Paltsev
Reviewed-by: Jagan Teki
23 Mar, 2018
5 commits
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Current DW SPI driver uses 32 bit access for some registers and
16 bit access for others. So if DW SPI IP is connected via bus
which doesn't support 16 bit access we will get bus error.Fix that by switching to 32 bit access only instead of 16 and 32 bit mix
Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1][1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Signed-off-by: Eugeniy Paltsev
Reviewed-by: Jagan Teki -
DW SPI internal chip select management has limitation:
it hold CS line in active state only when the FIFO is not
empty. If the FIFO freed before we add new data the SPI transaction will
be broken.So add option to use external gpio for chip select. Gpio can be added
via device tree using standard gpio bindings.Signed-off-by: Eugeniy Paltsev
Reviewed-by: Jagan Teki -
There is no sense in waiting for RX data in dw_reader function:
there is no chance that RX data will appear in RX FIFO if
RX FIFO is empty after previous TX write in dw_writer function.
So get rid of this waiting. After that we can get rid of dw_reader
return value and make it returning void. After that we can get rid
of dw_reader return value check in poll_transfer function.With these changes we're getting closer to Linux DW SPI driver.
Signed-off-by: Eugeniy Paltsev
Reviewed-by: Jagan Teki -
In current implementation we get -ETIMEDOUT error when we try to use
transmit only mode (SPI_TMOD_TO)
This happens because in transmit only mode input FIFO never gets any data
which breaks our logic in dw_reader(): we are waiting until RX data will be
ready in dw_reader, but this newer happens, so we return with error.Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use
RX FIFO.Signed-off-by: Eugeniy Paltsev
Reviewed-by: Jagan Teki -
In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.Signed-off-by: Eugeniy Paltsev
Reviewed-by: Jagan Teki
26 Jan, 2018
1 commit
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Add option to set spi controller clock frequency via device tree
using standard clock bindings.Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)Reviewed-by: Marek Vasut
Signed-off-by: Eugeniy Paltsev
Reviewed-by: Jagan Teki
01 Jun, 2017
1 commit
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These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.In the end we will have:
1. dev_read_addr...() - works on devices, supports flat/live tree
2. devfdt_get_addr...() - current functions, flat tree only
3. of_get_address() etc. - new functions, live tree onlyAll drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: Simon Glass
08 Feb, 2017
1 commit
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At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.Signed-off-by: Simon Glass
28 Oct, 2015
2 commits
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Replace numeric mask hexcodes with GENMASK macro
in designware_spiCc: Stefan Roese
Cc: Marek Vasut
Reviewed-by: Tom Rini
Signed-off-by: Jagan Teki -
Replace numerical bit shift with BIT macro
in designware_spi:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31Cc: Stefan Roese
Cc: Marek Vasut
Reviewed-by: Tom Rini
Signed-off-by: Jagan Teki
31 Aug, 2015
1 commit
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This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.Signed-off-by: Simon Glass
Reviewed-by: Joe Hershberger
Acked-by: Stephen Warren
30 Mar, 2015
1 commit
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By specification the FIFO size would be in a range 2-256 bytes. From TX Level
prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes.
Hence there are currently two issues:
a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
either 0 or 1 byte;
b) FIFO size is incorrectly decreased by 1 which already done by meaning of
TX Level register.Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth)
Signed-off-by: Andy Shevchenko
Signed-off-by: Axel Lin
Acked-by: Pavel Machek
Reviewed-by: Jagannadha Sutradharudu Teki
30 Jan, 2015
1 commit
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This is common to all SPI drivers and specifies a structure used by the
uclass. It makes more sense to define it in the uclass.Reviewed-by: Masahiro Yamada
Signed-off-by: Simon Glass
06 Jan, 2015
2 commits
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Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Stefan Roese
Cc: Vince Bridgers
Reviewed-by: Stefan Roese
Acked-by: Pavel Machek
Reviewed-by: Jagannadha Sutradharudu Teki -
Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary
to test fifo == 257. In the case fifo is 257, it means the latest valid
setting is fifo = 256. So after the for loop iteration, we should check
fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.
This patch fixes above issues.Signed-off-by: Axel Lin
Acked-by: Stefan Roese
Reviewed-by: Jagannadha Sutradharudu Teki
06 Dec, 2014
2 commits
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As suggested by Pavel, here some fixes to the designware SPI driver:
- Spelling fixes
- Comment for timeout added
- Removed n_bytes completely (bits_per_word is enough for this)
- Unput clock now not defined via macro. The function to
get the clock value is now called directly from within the driverSigned-off-by: Stefan Roese
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Vince Bridgers
Cc: Marek Vasut
Acked-by: Pavel Machek
Cc: Jagannadha Sutradharudu Teki -
This patch adds the driver for the Designware master SPI controller. This
IP core is integrated on the Altera SoCFPGA. This implementation is a
driver model (DM) implementation. So multiple SPI drivers can be used.
Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller
used to connect the SPI NOR flashes. Without DM, using multiple SPI
drivers is not possible.This driver is very loosely based on the Linux driver. Most of the Linux
driver is removed. Only the polling loop for the transfer is really used
from this driver, as we don't support interrupts and DMA right now.This is tested on the SoCrates SoCFPGA board using the SPI pins on the
P14 header.Signed-off-by: Stefan Roese
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Vince Bridgers
Cc: Marek Vasut
Cc: Pavel Machek
Reviewed-by: Simon Glass
Cc: Jagannadha Sutradharudu Teki
