25 Sep, 2014

4 commits

• 8aeb893a8   ARMv8/ls2085a: Move u-boot location to make room for RCW ... Browse Code »

  When booting with SP, RCW resides at the beginning of IFC NOR flash.

  Signed-off-by: York Sun

  York Sun

  2014-09-25 23:36:19 +0800  
• 8bfa301b0   ARMv8/ls2085a: Enable secondary cores ... Browse Code »

  Spin table is at the very beginning of boot code. Each core has an individual
  release address within the spin table, the ft_cpu_setup fn updates the
  "cpu-release-addr" property of each cpu node with the corresponding release
  address.

  Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.

  Signed-off-by: York Sun
  Signed-off-by: Arnab Basu

  York Sun

  2014-09-25 23:36:19 +0800  
• d9c68b144   ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory block ... Browse Code »

  DP-DDR is used for DPAA, separated from main memory pool for general
  use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).

  Signed-off-by: York Sun

  York Sun

  2014-09-25 23:36:18 +0800  
• e211c12e7   board/ls2085a: Add support of NOR and NAND flash for simulator ... Browse Code »

  Add support of NOR and NAND flash for simulator target.
  Here
  IFC - CS0: NOR flash
  IFC - CS1: NAND flash

  Signed-off-by: Prabhakar Kushwaha
  Reviewed-by: York Sun

  Prabhakar Kushwaha

  2014-09-25 23:36:17 +0800  

05 Jul, 2014

1 commit

• f749db3a7   ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support ... Browse Code »

  LS2085A is an ARMv8 implementation. This adds board support for emulator
  and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)

  Signed-off-by: York Sun
  Signed-off-by: Arnab Basu
  Signed-off-by: J. German Rivera
  Signed-off-by: Bhupesh Sharma

  York Sun

  2014-07-05 01:48:41 +0800