06 Aug, 2016
7 commits
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We no longer need to set 'caps' as it's not passed to sdhci_setup_cfg
anymore.Fixes: 14bed52d276a ("mmc: sdhci: remove the unnecessary arguments for
sdhci_setup_cfg")
Signed-off-by: Tom Rini -
The already available ilog2 function does exactly the same in the common
case than the log2 function the current clock-driver reimplement.
So, simply move to that one.Signed-off-by: Heiko Stuebner
Acked-by: Simon Glass -
MMC core will use 400KHz for card initialize first and then switch to
higher frequency like 50MHz, we need to support both 400KHz and about
50MHz for dwmmc controller.Signed-off-by: Kever Yang
Acked-by: Simon Glass -
With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.Suggested-by: Simon Glass
Signed-off-by: Heiko Stuebner
Acked-by: Simon Glass
Updated for rk3399:
Signed-off-by: Simon Glass -
This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driverSigned-off-by: Kever Yang
Acked-by: Simon Glass
05 Aug, 2016
14 commits
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When disabled CONFIG_MMC_SDMA, variable caps didn't use.
This patch fixes the compiler error for -Wunused-but-set-variableSigned-off-by: Jaehoon Chung
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This patch fixes data starvation by host timeout(HTO) error interrupt
which occurred under FIFO mode transfer on rk3036 board.The former implement, the actual bytes were transmitted may be less than
should be. The size will still subtract value of len in case of there is
no receive/transmit FIFO data request interrupt.Signed-off-by: Ziyuan Xu
Acked-by: Jaehoon Chung
Reviewed-by: Simon Glass
Signed-off-by: Jaehoon Chung -
The former implement, dw_mmc will push and pop the redundant data to
FIFO, we should transfer it according to the real size.Signed-off-by: Ziyuan Xu
Acked-by: Jaehoon Chung
Reviewed-by: Simon Glass
Reviewed-by: Shawn Lin
Signed-off-by: Jaehoon Chung -
Some arguments don't need to pass to sdhci_setup_cfg.
Generic variable can be used in sdhci_setup_cfg, and some arguments are
already included in sdhci_host struct.It's enough that just pass the board specific things to sdhci_setup_cfg().
After removing the unnecessary arguments, it's more simpler than before.
It doesn't consider "Version" and "Capabilities" anymore in each SoC
driver.Signed-off-by: Jaehoon Chung
Reviewed-by: Simon Glass -
buswidth isn't used anywhere in sdhci_setup_cfg.
Signed-off-by: Jaehoon Chung
Reviewed-by: Minkyu Kang
Reviewed-by: Simon Glass -
This "commit 429790026021d522d51617217d4b86218cca5750" is wrong.
SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit.For example, Exynos didn't have CTRL_HISPD. But Highspeed mode
is supported.
(This quirks doesn't mean that driver didn't support the Highseepd mode.)Note: If driver didn't support the Highspeed Mode, use or add the other
quirks.After applied this patch, all Exynos SoCs are just running with 25MHz.
Signed-off-by: Jaehoon Chung
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It's nicer to see this:
=> mmc list
dwmmc@ff0c0000: 0
dwmmc@ff0f0000: 1 (eMMC)than this:
=> mmc list
dwmmc@ff0c0000: 0dwmmc@ff0f0000: 1 (eMMC)With the former, it's much clearer which mmc devices are on.
Signed-off-by: Ziyuan Xu
Acked-by: Simon Glass
Reviewed-by: Jaehoon Chung
Tested-by: Jaehoon Chung
Signed-off-by: Jaehoon Chung -
Use the generic error number instead of specific error number.
If use the generic error number, it can debug more easier.Signed-off-by: Jaehoon Chung
Reviewed-by: Simon Glass
Reviewed-by: Minkyu Kang -
"mmc.h" is already included. It's duplicated.
Signed-off-by: Jaehoon Chung
Reviewed-by: Simon Glass -
is already included in .
It can use instead ofSigned-off-by: Jaehoon Chung
Reviewed-by: Simon Glass -
Unset the SDHCI_QUIRK_BROKEN_R1B for exynos SoC.
(Tested on Exynos4 Boards.)Signed-off-by: Jaehoon Chung
Acked-by: Lukasz Majewski
Tested-by: Lukasz Majewski -
There is no data, it doesn't needs to wait for completing data transfer.
(It seems that it can be removed.)
Almost all timeout error is occured from stop command without data.
After applied this patch, I hope that we don't need to increase timeout value anymore.Signed-off-by: Jaehoon Chung
Acked-by: Lukasz Majewski
Tested-by: Lukasz Majewski
Acked-by: Minkyu Kang -
The current timeout detection logic is not very nice; it calls
get_timer(start) in the while() loop, and then calls it again after
the loop to check if a timeout error happened.Because of the time difference between the two calls of get_timer(),
the timeout detected after the loop may not be true.Signed-off-by: Masahiro Yamada
Acked-by: Jaehoon Chung
Signed-off-by: Jaehoon Chung -
The DT binding for the Tegra186 HSP module apparently wasn't quite final
when I posted initial U-Boot support for it. Add the final DT binding doc
and adapt all code and DT files to match it.Signed-off-by: Stephen Warren
Reviewed-by: Simon Glass
Signed-off-by: Tom Warren
03 Aug, 2016
3 commits
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Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.Signed-off-by: York Sun
Reported-by: Thomas Schaefer -
Update blob cmd to accept 64bit source, key modifier and destination
addresses. Also correct output result print format for fsl specific
implementation of blob cmd.Signed-off-by: Sumit Garg
Reviewed-by: York Sun -
Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);Signed-off-by: Yunhui Cui
Reviewed-by: York Sun
01 Aug, 2016
3 commits
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This fixes the following CACHE warnings when using sun8i_emac:
=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)Note this commit also changes the max rx size from 2024 to 2044,
matching what the kernel driver uses.Cc: Chen-Yu Tsai
Cc: Corentin LABBE
Cc: Amit Singh Tomar
Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver
model")
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Hans de Goede
31 Jul, 2016
2 commits
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Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers. In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed. The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.Signed-off-by: John Keeping
Reviewed-by: Kever Yang -
Not like the mmc-legacy which the devnum starts from 1, it starts from 0
in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num().Signed-off-by: Kever Yang
Acked-by: Simon Glass
Reviewed-by: Jaehoon Chung
30 Jul, 2016
6 commits
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According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
Reviewed-by: Jagan Teki
Reviewed-by: Mugunthan V N -
Add AT25DF321 flash support.
Fix AT25DF321A device name.Signed-off-by: Wenyou Yang
Reviewed-by: Jagan Teki -
As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.Signed-off-by: Vignesh R
Reviewed-by: Jagan Teki
Reviewed-by: Mugunthan V N -
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.Signed-off-by: Vignesh R
Reviewed-by: Jagan Teki
Reviewed-by: Mugunthan V N -
Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).Signed-off-by: Vignesh R
Reviewed-by: Jagan Teki
Reviewed-by: Mugunthan V N -
This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.Signed-off-by: Moritz Fischer
Reviewed-by: Jagan Teki
28 Jul, 2016
5 commits
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Signed-off-by: Tim Harvey
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It's no need to speed 10 seconds to wait the mmc device out from busy
status. 500 milliseconds enough.Signed-off-by: Ziyuan Xu
Reviewed-by: Jaehoon Chung
Tested-by: Jaehoon Chung -
Many SoCs allow power to be applied to or removed from portions of the SoC
(power domains). This may be used to save power. This API provides the
means to control such power management hardware.Signed-off-by: Stephen Warren
Acked-by: Simon Glass
