21 Jul, 2018
1 commit
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Following next kernel rcc bindings, we must use a MFD
RCC driver which is able to bind both clock and reset
drivers.We can reuse and adapt RCC MFD driver already available
for MCU SoCs (F4/F7/H7).Signed-off-by: Patrice Chotard
Signed-off-by: Patrick Delaunay
08 May, 2018
1 commit
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On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.Signed-off-by: Patrice Chotard
Tested By: Bruno Herrera
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
14 Mar, 2018
1 commit
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For timer clock, an additionnal prescaler is used which was
not taken into account previously.Signed-off-by: Patrice Chotard
30 Nov, 2017
3 commits
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In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.hSigned-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha -
MMC block needs 48Mhz source clock, for that we choose
to select the SAI PLL.
Update also stm32_clock_get_rate() to retrieve the MMC
clock source needed in MMC driver.STM32F4 uses a different RCC variant than STM32F7. For STM32F4
sdmmc clocks bit are located into dckcfgr register whereas there
are located into dckcfgr2 registers on STM32F7.
In both registers, bits CK48MSEL and SDMMC1SEL are located at
the same position.Signed-off-by: Christophe Priouzeau
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha -
Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha