17 Oct, 2013

1 commit

• 0dd38a35f   powerpc: Fix CamelCase warnings in DDR related code ... Browse Code »

  Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
  has various parameters with embedded acronyms capitalized that trigger the CamelCase
  warning in checkpatch.pl

  Convert those variable names to smallcase naming convention and modify all files
  which are using these structures with modified structures.

  Signed-off-by: Priyanka Jain

  Priyanka Jain

  2013-10-17 07:15:16 +0800  

15 Oct, 2013

1 commit

• 93e145964   Coding Style cleanup: replace leading SPACEs by TABs ... Browse Code »

  Signed-off-by: Wolfgang Denk
  [trini: Drop changes for PEP 4 following python tools]
  Signed-off-by: Tom Rini

  Wolfgang Denk

  2013-10-15 04:06:54 +0800  

24 Aug, 2012

1 commit

• 73b5396b2   powerpc/mpc8xxx: Add fine timing support for DDR3 ... Browse Code »

  When the DDR3 speed goes higher, we need to utilize fine offset
  from SPD.

  Signed-off-by: York Sun
  Signed-off-by: Andy Fleming

  York Sun

  2012-08-24 01:16:55 +0800  

29 Nov, 2011

1 commit

• 2f3a71f23   mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification ... Browse Code »

  Newer JEDEC DDR3 SPD Specifications define several additional values for
  the DDR3 module_type field which were undefined when this code was
  written. Update the code to handle the newer module types.

  Signed-off-by: Ira W. Snyder
  Cc: York Sun
  Signed-off-by: Kumar Gala

  Ira W. Snyder

  2011-11-29 22:48:06 +0800  

12 Jul, 2011

1 commit

• c49290cd1   Adding more SPD registers ... Browse Code »

  Adding byte 32 and 33

  Signed-off-by: York Sun
  Signed-off-by: Kumar Gala

  York Sun

  2011-07-12 02:24:20 +0800  

04 Apr, 2011

1 commit

• c7fd27ccf   mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements ... Browse Code »

  The numeric constants in the switch statements are replaced by #defines
  added to the common ddr_spd.h header. This dramatically improves the
  readability of the switch statments.

  In addition, a few of the longer lines were cleaned up, and the DDR2
  type for an SO-RDIMM module was added to the DDR2 switch statement.

  Signed-off-by: Kyle Moffett
  Cc: Andy Fleming
  Cc: Kim Phillips
  Acked-by: York Sun
  Signed-off-by: Kumar Gala

  Kyle Moffett

  2011-04-04 22:24:43 +0800  

27 Jul, 2010

1 commit

• 9490ff486   powerpc/8xxx: Enable DDR3 RDIMM support ... Browse Code »

  Enabled registered DIMMs using data from SPD. RDIMMs have registers
  which need to be configured before using. The register configuration
  words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
  should read those RCWs and put into DDR controller before initialization.

  Signed-off-by: York Sun

  york

  2010-07-27 02:16:10 +0800  

31 Mar, 2009

1 commit

• c360ceac0   fsl-ddr: add the DDR3 SPD infrastructure ... Browse Code »

  - support mirrored DIMMs, not support register DIMMs
  - test passed on P2020DS board with MT9JSF12872AY-1G1D1
  - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1

  Signed-off-by: Dave Liu
  Signed-off-by: Travis Wheatley

  Dave Liu

  2009-03-31 02:33:50 +0800  

27 Aug, 2008

1 commit

• 0f2cbe3f5   Add proper SPD definitions for DDR1/2/3 ... Browse Code »

  Also adds helper functions for DDR1/2 to verify the checksum.

  Signed-off-by: Kumar Gala

  James Yang

  2008-08-27 08:05:53 +0800