29 Jan, 2016

2 commits

  • You can now configure LAG on VSC9953's ports using the command:
    ethsw [port ] aggr {[help] | show | }

    A port must belong to a single LAG. By default, a port
    belongs to a LAG equal to the port's number.

    For each frame, a hash will be calculated based on
    Source/Destination MAC addresses, Source/Destination IP(v4/v6)
    addresses, Source/Destination ports. This hash will be used to
    select a single egress port from LAG. This also assures
    that frames from the same flow will always have the
    same egress port.

    Signed-off-by: Codrin Ciubotariu
    Acked-by: Joe Hershberger

    Codrin Ciubotariu
     
  • The driver for VSC9953 L2 switch IP supports many features and
    the documentation needs to be updated.

    Signed-off-by: Codrin Ciubotariu
    Acked-by: Joe Hershberger

    Codrin Ciubotariu
     

17 Jan, 2015

1 commit

  • This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP
    is integrated in Freescale T1040 and T1020 SoCs.
    The L2 switch has 10 Ethernet ports: 2 internal fixed-links
    (ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps.
    The external ports may be connected to PHYs over QSGMII and SGMII.

    Commands have also been added to enable/disable a port and to
    check a port's link speed, duplexity and status. The commands are:

    ethsw port enable|disable - enable/disable an l2 switch port
    ethsw port show - show an l2 switch port's configuration

    port_nr=0..9; use "all" for all ports

    For more detailse please see doc/README.t1040-l2switch

    Signed-off-by: Codrin Ciubotariu
    Acked-by: Joe Hershberger
    Reviewed-by: York Sun

    Codrin Ciubotariu