10 Oct, 2013
2 commits
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This matches the 64 bit size in struct mtd_info and allows the mtdparts
command to function correctly with a flash >= 4GiB. Format specifiers
for size & offset are given the ll length, matching its use in
drivers/mtd in absence of something like inttypes.h/PRIx64.Signed-off-by: Paul Burton
Acked-by: Stefan Roese -
Linux modified the MTD driver interface in commit edbc4540 (with the
same name as this commit). The effect is that calls to mtd_read will
not return -EUCLEAN if the number of ECC-corrected bit errors is below
a certain threshold, which defaults to the strength of the ECC. This
allows -EUCLEAN to stop indicating "some bits were corrected" and begin
indicating "a large number of bits were corrected, the data held in
this region of flash may be lost soon". UBI makes use of this and when
-EUCLEAN is returned from mtd_read it will move data to another block
of flash. Without adopting this interface change UBI on U-boot attempts
to move data between blocks every time a single bit is corrected using
the ECC, which is a very common occurance on some devices.For some devices where bit errors are common enough, UBI can get stuck
constantly moving data around because each block it attempts to use has
a single bit error. This condition is hit when wear_leveling_worker
attempts to move data from one PEB to another in response to an
-EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is
called to perform the data copy, and after the data is written it is
read back to check its validity. If that read returns UBI_IO_BITFLIPS
(in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to
wear_leveling worker, which then proceeds to schedule the destination
PEB for erasure. This leads to erase_worker running on the PEB, and
following a successful erase wear_leveling_worker is called which
begins this whole cycle all over again. The end result is that (without
UBI debug output enabled) the boot appears to simply hang whilst in
reality U-boot busily works away at destroying a block of the NAND
flash. Debug output from this situation:UBI DBG: ensure_wear_leveling: schedule scrubbing
UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027
UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096
UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083
UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data
UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192
UBI: fixable bit-flip detected at PEB 1027
UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096
UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083
UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192
UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192
UBI: fixable bit-flip detected at PEB 4083
UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0
UBI DBG: erase_worker: erase PEB 4083 EC 55
UBI DBG: sync_erase: erase PEB 4083, old EC 55
UBI DBG: do_sync_erase: erase PEB 4083
UBI DBG: sync_erase: erased PEB 4083, new EC 56
UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0
UBI DBG: ensure_wear_leveling: schedule scrubbing
UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
...This patch adopts the interface change as in Linux commit edbc4540 in
order to avoid such situations. Given that none of the drivers under
drivers/mtd return -EUCLEAN, this should only affect those using
software ECC. I have tested that it works on a board which is
currently out of tree, but which I hope to be able to begin
upstreaming soon.Signed-off-by: Paul Burton
Acked-by: Stefan Roese
08 Oct, 2013
1 commit
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As documented, almost all U-Boot commands expect numbers to be entered
in hexadecimal input format. (Exception: for historical reasons, the
"sleep" command takes its argument in decimal input format.)This rule was broken for the "load" command; for details please see
especially commits 045fa1e "fs: add filesystem switch libary,
implement ls and fsload commands" and 3f83c87 "fs: fix number base
behaviour change in fatload/ext*load". In the result, the load
command would always require an explicit "0x" prefix for regular
(i. e. base 16 formatted) input.Change this to use the standard notation of base 16 input format.
While strictly speaking this is a change of the user interface, we
hope that it will not cause trouble. Stephen Warren comments (see
[1]):I suppose you can change the behaviour if you want; anyone
writing "0x..." for their values presumably won't be
affected, and if people really do assume all values in U-Boot
are in hex, presumably nobody currently relies upon using
non-prefixed values with the generic load command, since it
doesn't work like that right now.[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/171172
Acked-by: Tom Rini
Acked-by: Stephen Warren
Signed-off-by: Wolfgang Denk
07 Oct, 2013
6 commits
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Forcibly set hose->pci_prefetch to NULL to make sure it will be setup.
This will help if for any reason callers didn't make sure themselves to
NULL the field.Signed-off-by: Thierry Reding
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The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S}
predates the SPDX conversion, so the original elaborate license
statements sneaked in.
Fix this by replacing them with the proper abbreviation.Signed-off-by: Andre Przywara
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Signed-off-by: Otavio Salvador
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The modelist data uses the list definition but the 'list.h' header
were not being included. The build failure is bellow:,----
| In file included from yyyy.c:16:0:
| .../u-boot/include/linux/fb.h:503:19: error: field 'modelist' has incomplete type
| struct list_head modelist; /* mode list */
| ^
| make[1]: *** [yyyy.o] Error 1
| make[1]: Leaving directory `.../u-boot/board/xxx/yyyy'
| make: *** [board/xxx/yyyy/libyyyy.o] Error 2
`----Signed-off-by: Otavio Salvador
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The part_validate comment had a wrong description of the actions it
does and referenced to non-existent functions while in fact it calls
'part_validate_eraseblock()'.Signed-off-by: Otavio Salvador
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This patch prevents data abort when pmic bat command is called
on non-batery pmic device.Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
CC: Lukasz Majewski
CC: Minkyu Kang
05 Oct, 2013
1 commit
04 Oct, 2013
7 commits
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To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the VExpress specific
manner.
There is no need to provide a custom smp_waitloop() function here.This also serves as an example for what to do when adding support for
new boards.Signed-off-by: Andre Przywara
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For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.Signed-off-by: Andre Przywara
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Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.Signed-off-by: Andre Przywara
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To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.Signed-off-by: Andre Przywara
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The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0xFFFFFFFF)The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara
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While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.Signed-off-by: Andre Przywara
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A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.Signed-off-by: Andre Przywara
03 Oct, 2013
2 commits
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armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.Signed-off-by: Andre Przywara
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Signed-off-by: Tom Rini
02 Oct, 2013
6 commits
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There are a few make options such as BUILD_TAG which can be provided when
building U-Boot. Provide a way for buildman to pass these flags to make
also.The flags should be in a [make-flags] section and arranged by target name
(the 'target' column in boards.cfg. See the README for more details.Signed-off-by: Simon Glass
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Commit 27af930e9a5c91365ca639ada580b338eabe4989 changed the boards.cfg format
but missed to change the parsing in buildman. A follow-on commit
03c1bb242548e4e9d267d784861ccd69a1887aa0 fixed this but missed fixing the
tests.This patch updates the tests to fit the new Board constructor.
./tools/buildman/buildman -t
Signed-off-by: Simon Glass
27 Sep, 2013
7 commits
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The EHCI controller has some very specific requirements for the USB 2.0
port test modes, which were not closely followed in the initial test
mode commit. It demands that the host controller is completely shut down
(all ports suspended, Run/Stop bit unset) when activating test mode, and
will not work on an already enumerated port.This patch fixes that by introducing a new ehci_shutdown() function that
closely follows the procedure listed in EHCI 4.14. Also, when we have
such a function anyway, we might as well also use it in
usb_lowlevel_stop() to make the normal host controller shutdown cleaner.Signed-off-by: Julius Werner
Acked-by: Simon Glass -
This patch adds the pad to i.MX6DQ and changes the i.MX6DLS
declaration to match the Linux kernel declaration.Signed-off-by: Eric Nelson
Acked-by: Marek Vasut -
The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize
the CCGR3 register caused an undefined value for CG0.Signed-off-by: Pierre Aubert
CC: Stefano Babic
Acked-by: Eric Nelson -
If smc911x_initialize() fails we should return the error immediately.
While at it, also check the error from cpu_eth_init().
Signed-off-by: Fabio Estevam
Acked-by: Stefano Babic -
If cpu_eth_init() fails we should return the error immediately.
Cc: Marek Vasut
Signed-off-by: Fabio Estevam
Acked-by: Marek Vasut -
If cpu_eth_init() fails we should return the error immediately.
Signed-off-by: Fabio Estevam
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Convert set_hdr_func(struct imx_header *imxhdr) to set_hdr_func(void)
to get rid of the warningwarning: ‘imxhdr’ is used uninitialized in this function
Signed-off-by: York Sun
Acked-by: Stefano Babic
24 Sep, 2013
8 commits
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When unbind the gadget driver, need call disconnect first.
Signed-off-by: Bo Shen
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The download gadget code and DFU function lacks of proper declarations
for the case when a target board wants to use only one of available usb
functions.Moreover the relevant declarations have been moved to consistent
localization (like ).Signed-off-by: Lukasz Majewski
Cc: Marek Vasut -
Only the requires error.h include. Hence, several
includes of error.h at USB gadget functions are not needed.Moreover unnecessary malloc.h includes were also removed.
Signed-off-by: Lukasz Majewski
Cc: Marek Vasut -
The mass storage composite function is now compiled in only when
CONFIG_USB_GADGET_MASS_STORAGE is defined.
Such change provides binary size reduction for boards which use USB
download gadget (like am335x_evm) with DFU, but don't use UMS.For example at am335x_evm board reduction is more than 2KiB for
text and around 120B for data.Signed-off-by: Lukasz Majewski
Cc: Marek Vasut -
Enable DFU for RAM, provide example dfu_alt_info
Signed-off-by: Afzal Mohammed
Cc: Heiko Schocher
Cc: Tom Rini
Cc: Marek Vasut
Cc: Lukasz Majewski
Cc: Pantelis Antoniou
Reviewed-by: Lukasz Majewski -
DFU spec mentions it as a method to upgrade firmware (software stored
in writable non-volatile memory). It also says other potential uses of
DFU is beyond scope of the spec.Here such a beyond the scope use is being attempted - directly pumping
binary images from host via USB to RAM. This facility is a developer
centric one in that it gives advantage over upgrading non-volatile
memory for testing new images every time during development and/or
testing.Directly putting image onto RAM would speed up upgrade process. This and
convenience was the initial thoughts that led to doing this, speed
improvement over MMC was only 1 second though - 6 sec on RAM as opposed
to 7 sec on MMC in beagle bone, perhaps enabling cache and/or optimizing
DFU framework to avoid multiple copy for ram (if worth) may help, and
on other platforms and other boot media like NAND maybe improvement
would be higher.And for a platform that doesn't yet have proper DFU suppport for
non-volatile media's, DFU to RAM can be used.Another minor advantage would be to increase life of mmc/nand as it
would be less used during development/testing.usage: ram
eg. kernel ram 0x81000000 0x1000000Downloading images to RAM using DFU is not something new, this is
acheived in openmoko also.DFU on RAM can be used for extracting RAM contents to host using dfu
upload. Perhaps this can be extended to io for squeezing out register
dump through usb, if it is worth.Signed-off-by: Afzal Mohammed
Cc: Heiko Schocher
Cc: Marek Vasut
Cc: Lukasz Majewski
Cc: Pantelis Antoniou
Cc: Gerhard Sittig
Acked-by: Marek Vasut
Acked-by: Lukasz Majewski
Acked-by: Heiko Schocher -
MMC and NAND independently defines same enumerators for read/write.
Unify them by defining enum in dfu header. RAM support that is being
added newly also can make use of it.Signed-off-by: Afzal Mohammed
Cc: Heiko Schocher
Cc: Marek Vasut
Cc: Lukasz Majewski
Cc: Pantelis Antoniou
Acked-by: Lukasz Majewski
Acked-by: Marek Vasut
Acked-by: Heiko Schocher -
New dfu_init_env_entities() function has been extracted from cmd_dfu.c and
stored at dfu core.This is a dfu centric code, so it shall be processed in the core.
Change-Id: I756c5de922fa31399d8804eaadc004ee98844ec2
Signed-off-by: Lukasz Majewski
Tested-by: Heiko Schocher
