25 Mar, 2015
1 commit
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with WCR_WDW set, the watchdog won't trigger if we bootet linux and idle
around while the watchdog is not triggered. It seems the timer makes
progress very slowly if at all. I managed to remain 20minutes alive
while the timeout was set to 60secs. It reboots within 60secs if I start
a busyloop in userland (something like "while (1) { }").While I don't see a reason why the WDT should not be running while the
CPU is in idle, I'm dropping this bit.Signed-off-by: Sebastian Andrzej Siewior
Acked-by: Stefano Babic
20 Mar, 2015
1 commit
19 Mar, 2015
1 commit
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If the GBE bit is set, when do next time autonegotiation,
if the result is not 1000Mbps, it will fallback to 100Mbps
checking. So, we need to clear the GBE bit.Signed-off-by: Bo Shen
18 Mar, 2015
7 commits
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The current implementation for baudrate calculation is incorrect.
This part from the formula:"2 ^ (n + 1)" is not equivalent to (1 << n) but to (2 << n)!
This patch fixes this and moves this calculation to a function instead of using a macro.
This new function is taken from the Linux kernel.This was detected and tested on the Marvell Armada A38x DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese
Cc: Prafulla Wadaskar
Cc: Luka Perkov
Cc: Hans de Goede
Cc: Ian Campbell
Cc: Heiko Schocher
Acked-by: Hans de Goede -
Change addresses to unsigned long to be compatible with 64-bit builds.
Signed-off-by: Rob Herring
Cc: Heiko Schocher -
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.Signed-off-by: Rob Herring
Cc: Pantelis Antoniou -
Change addresses to unsigned long to be compatible with 64-bit builds.
Regardless of fixing warnings, the device is still only 32-bit capable.Signed-off-by: Rob Herring
Cc: Pantelis Antoniou -
SDHCI_HOST_CONTROL is a byte-sized register, so don't write to it
as if it were a long, as that would result in clobbering the three
registers following.Signed-off-by: Matt Reimer
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Properly mask SELBASECLK by using an actual mask rather than the
number of bits to shift in order to create the mask.Signed-off-by: Matt Reimer
Acked-by: Jaehoon Chung
17 Mar, 2015
1 commit
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Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
error register offset.Change the "char reserved3[59]" to "char reserved3[56]".
Signed-off-by: Peng Fan
Tested-by: Fabio Estevam
15 Mar, 2015
1 commit
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Panasonic's System LSI products, UniPhier SoC family, have been
transferred to Socionext Inc.Signed-off-by: Masahiro Yamada
10 Mar, 2015
2 commits
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This enables the musb glue layer to use the AXP221's VBUS detection
function to check for VBUS. This fixes otg support on the A23 q8h
tablets.Note that u-boot never calls musb_shutdown(), so once VBUS is enabled,
it is never disabled until the system is powered off, or the OS does
so. This can be used to our advantage to keep VBUS powered into the
OS, where support for AXP221 is not available yet.Fixes: 52defe8f6570 ("sunxi: musb: Check Vbus-det before enabling otg port power")
Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
Some of the AXP PMICs support VBUS detection, i.e. checking whether
VBUS power input is available and usable (supplied by an external
source). A few boards use this instead of a separate GPIO to detect
VBUS on USB OTG.Signed-off-by: Chen-Yu Tsai
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede
09 Mar, 2015
1 commit
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For writing files, DFU implementation requires the file buffer
with the len at least of file size. For big files it requires
the same big buffer.Previously the file buffer was allocated as a static variable,
so it was a part of U-Boot .bss section. For 32MiB len of buffer
we have 32MiB of additional space, required for this section.The .bss needs to be cleared after the relocation.
This introduces an additional boot delay at every start, but usually
the dfu feature is not required at the standard boot, so the buffer
should be allocated only if required.This patch removes the static allocation of this buffer,
and alloc it with memalign after first call of function:
- dfu_fill_entity_mmc()
and the buffer is freed on dfu_free_entity() call.This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~888ms - before this change (arch memset enabled for .bss clear)
- ~464ms - after this changeSigned-off-by: Przemyslaw Marczak
Reviewed-by: Simon Glass
Cc: Lukasz Majewski
Cc: Stephen Warren
Cc: Pantelis Antoniou
Cc: Tom Rini
Cc: Marek Vasut
08 Mar, 2015
1 commit
06 Mar, 2015
9 commits
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This strdup() is missing a check. Add it.
Signed-off-by: Simon Glass
Acked-by: Heiko Schocher -
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw
where 'hamming' is still the default.Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.Signed-off-by: Ash Charles
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Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
WAIT0 pin for determining whether the NAND is ready or not. This only
works if all NAND chips are connected to WAIT0. If some chips are
connected to the other available pin WAIT1, nand_wait() does not really
wait and prints a WARN_ON message.This patch allows the board to provide configuration of which chip is
connected to which WAITx signal. For example, one can define in
include/configs/foo.h:#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
This would mean that chips using to CS0 and 1 are connected to WAIT0 and
chips with CS2 and 3 are connected to WAIT1.Signed-off-by: Michal Sojka
Acked-by: Stefan Roese
Tested-by: Michal VokáčCc: Tom Rini
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Often on boards exists a circuit which switches power on/off to LCD display.
Due to the need of limiting the in-rush current the output voltage from this
circuit rises "slowly", so it is necessary to wait a bit (VCC ramp up time)
before starting output on LCD-pins.
This time is specified in ms within the panel-settings, called "pup_delay"Further some LCDs need a couple of frames to stabilize the image on it.
We have now the possibility to wait some time after starting output on LCD.
This time is also specified in ms within panel-settings, called "pon_delay"Signed-off-by: Hannes Petermaier
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The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.The API's for transition of Security states have been added
which will be used in case of SECURE BOOT.Signed-off-by: Ruchika Gupta
Signed-off-by: Gaurav Rana
Reviewed-by: York Sun -
Remove dependency of rsa_mod_exp from CONFIG_FIT_SIGNATURE.
As rsa modular exponentiation is an independent module
and can be invoked independently.Signed-off-by: Gaurav Rana
Acked-by: Simon Glass
Reviewed-by: York Sun -
- DMA threshold mode can be selected in board config head file.
Signed-off-by: Sonic Zhang
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Board can define its own AXI burst length to improve DWMAC DMA performance.
v2-changes:
- Avoid write burst len register when the Macro is not defined.v3-changes:
- Add axi_bus register member to struct eth_dma_regs.Signed-off-by: Sonic Zhang
Acked-by: Joe Hershberger
05 Mar, 2015
2 commits
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Use the full driver model GPIO and serial drivers in SPL now that these are
supported. Since device tree is not available they will use platform data.Remove the special SPL GPIO function as it is no longer needed.
This is all in one commit to maintain bisectability.
Signed-off-by: Simon Glass
02 Mar, 2015
6 commits
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Fix trivial typo.
Acked-by: Simon Glass
Signed-off-by: Axel Lin -
Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process, is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.Commands added
--------------
dek_blob - encapsulating DEK as a cryptgraphic blobCommands Syntax
---------------
dek_blob src dst lenEncapsulate and create blob of a len-bits DEK at
address src and store the result at address dst.Signed-off-by: Raul Cardenas
Signed-off-by: Nitin GargSigned-off-by: Ulises Cardenas
Signed-off-by: Ulises Cardenas-B45798
28 Feb, 2015
6 commits
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Support xHCI host driver used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada
Acked-by: Marek Vasut -
Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.Signed-off-by: Masahiro Yamada
Acked-by: Marek Vasut -
Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers. We still keep UART platform devices because they might
be useful for SPL.Signed-off-by: Masahiro Yamada
Acked-by: Marek Vasut -
We do not have to set the LCR register every time we change the
baud-rate. We just need to set it up once in the probe function.Signed-off-by: Masahiro Yamada
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For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11)
is not working correctly. As a side effect, it also modifies MCR
register (offset = 0x10) and results in unexpected behavior.Signed-off-by: Masahiro Yamada
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Since commit 0e7368c6c426 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include with
so we do not need to create the symbolic link during the
build.Signed-off-by: Masahiro Yamada
26 Feb, 2015
1 commit
