20 Jan, 2020

2 commits


06 Dec, 2019

5 commits

  • The board has both VDD_SOC_IN and VDD_ARM_IN rails connected to the same
    PMIC rail, align the LDO voltages to avoid leaking inside the MX6SX SoC.

    Signed-off-by: Marek Vasut
    Cc: Fabio Estevam
    Cc: Silvio Fricke
    Cc: Stefano Babic

    Marek Vasut
     
  • Ever since the conversion to DM PCI, the board was missing the PCIe DT
    nodes, hence the PCI did not really work. Fill in the DT nodes and add
    missing PCIe device reset.

    Moreover, bring the PCIe power domain up before booting Linux. This is
    mandatory to keep old broken vendor kernels working, as they do not do
    so and depend on the bootloader to bring the power domain up.

    Signed-off-by: Marek Vasut
    Cc: Fabio Estevam
    Cc: Silvio Fricke
    Cc: Stefano Babic

    Marek Vasut
     
  • Convert the board to ethernet DM support. Adjust board file accordingly,
    as the board_eth_init() contains custom clock configuration required for
    this board to work. Furthermore, enable FEC1 clock to make FEC1 work as
    well.

    Signed-off-by: Marek Vasut
    Cc: Fabio Estevam
    Cc: Silvio Fricke
    Cc: Stefano Babic

    Marek Vasut
     
  • Enable DRAM calibration in SPL to improve behavior of the board
    in edge conditions of the thermal envelope of the board and make
    it even more stable.

    Signed-off-by: Marek Vasut
    Cc: Fabio Estevam
    Cc: Silvio Fricke
    Cc: Stefano Babic

    Marek Vasut
     
  • In preparation for use of DDR DRAM fine-tuning upon boot,
    convert the board to SPL framework instead of using DCD
    tables to bring up DRAM and pinmux.

    Signed-off-by: Marek Vasut
    Cc: Fabio Estevam
    Cc: Silvio Fricke
    Cc: Stefano Babic

    Marek Vasut
     

03 Dec, 2019

3 commits


10 Oct, 2019

3 commits


12 Aug, 2019

2 commits


23 Jun, 2019

1 commit


11 Jun, 2019

4 commits