08 Apr, 2019

1 commit

  • This patch moves all instances of static "watchdog_dev" declarations to
    the "data" section. This may be needed, as the BSS may not be cleared
    in the early U-Boot phase, where watchdog_reset() is already beeing
    called. This may result in incorrect pointer access, as the check to
    "!watchdog_dev" in watchdog_reset() may not be true and the function
    may continue to run.

    Signed-off-by: Stefan Roese
    Cc: Heiko Schocher
    Cc: Tom Rini
    Cc: Michal Simek
    Cc: "Marek Behún"
    Cc: Daniel Schwierzeck
    Tested-by: Michal Simek (on zcu100)
    Reviewed-by: Michal Simek

    Stefan Roese
     

15 Feb, 2019

1 commit

  • distro boot expects that fdtfile name is setup for alternative DTB.
    Create this file based on the first platform compatible string.
    This should ensure that one rootfs can store multiple DTBs for different
    boards.
    Reflect structure which is used in Linux kernel. It means dtbs are
    strored in xilinx folder.

    Signed-off-by: Michal Simek
    Reviewed-by: Alexander Graf

    Michal Simek
     

14 Feb, 2019

6 commits


24 Jan, 2019

3 commits


30 Nov, 2018

4 commits

  • For testing purpose use zcu102 which has SD at controller 1 and this can
    be used for testing this mini configuration.

    U-Boot 2018.11-00279-gdc482e7ee092 (Nov 30 2018 - 10:22:56 +0100)

    Model: ZynqMP MINI EMMC1
    Board: Xilinx ZynqMP
    DRAM: 512 MiB
    EL Level: EL3
    MMC: sdhci@ff170000: 0
    In: dcc
    Out: dcc
    Err: dcc
    ZynqMP>

    Signed-off-by: Michal Simek

    Michal Simek
     
  • For testing purpose use zcu100 which has SD at controller 0 and this can
    be used for testing this mini configuration.

    U-Boot 2018.11-00281-gc5d48466e76e (Nov 30 2018 - 10:41:05 +0100)

    Model: ZynqMP MINI EMMC0
    Board: Xilinx ZynqMP
    DRAM: 512 MiB
    EL Level: EL3
    MMC: sdhci@ff160000: 0
    In: dcc
    Out: dcc
    Err: dcc
    ZynqMP>

    Signed-off-by: Michal Simek

    Michal Simek
     
  • If only usb ethernet gadget is enabled it can start automatically.
    If more gagdets are enabled usb ethernet gadget can be bind by
    "bind /amba/usb1@ff9e0000/dwc3@fe300000 usb_ether" (on zcu100)

    Signed-off-by: Michal Simek

    Michal Simek
     
  • This configuration is useful when you want to run small u-boot and
    perform DDR memory test to make sure that DDR is properly configured.
    It is use for board bringup because alternative u-boot memory tests is
    quite good.
    Configuration is running out of OCM.

    As is done for others mini configurations 0x80 bytes for variables is
    enough and only default variables are stored there.

    Alternative memtest is enabled and also 2GB of DDR via DTS files.
    Configuration is enabling ZYNQMP_PSU_INIT_ENABLED and include psu_init()
    from zcu102 for testing purpose.
    In case of size issue this can be moved to SPL configuration as is done
    for mini_qspi configuration but it is not a problem now.

    Log:
    U-Boot 2018.11-00268-gbd58b8ba8915 (Nov 29 2018 - 15:33:35 +0100)

    Model: ZynqMP MINI
    Board: Xilinx ZynqMP
    DRAM: WARNING: Initializing TCM overwrites TCM content
    2 GiB
    EL Level: EL3
    In: dcc
    Out: dcc
    Err: dcc
    ZynqMP>

    Signed-off-by: Michal Simek

    Michal Simek
     

29 Nov, 2018

2 commits


26 Nov, 2018

3 commits


16 Oct, 2018

3 commits

  • This patch adds new zynqmp command "zynqmp tcminit mode" to
    initialize TCM. TCM needs to be initialized before accessing
    to avoid ECC errors. This new command helps to perform
    the same. It also makes tcm_init() as global and uses it for
    doing the TCM initialization.

    Signed-off-by: Siva Durga Prasad Paladugu
    Signed-off-by: Michal Simek

    Siva Durga Prasad Paladugu
     
  • Xilinx is introducing Versal, an adaptive compute acceleration platform
    (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
    Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
    Engines with leading-edge memory and interfacing technologies to deliver
    powerful heterogeneous acceleration for any application. The Versal AI
    Core series has five devices, offering 128 to 400 AI Engines. The series
    includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
    Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
    than 1,900 DSP engines optimized for high-precision floating point with
    low latency.

    The patch is adding necessary infrastructure in place without enabling
    platform which is done in separate patch.

    Signed-off-by: Michal Simek

    Michal Simek
     
  • Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
    USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

    Boards have mix of Winbond/ST QSPIs.

    Signed-off-by: Michal Simek

    Michal Simek
     

26 Sep, 2018

1 commit


07 Aug, 2018

1 commit


06 Aug, 2018

3 commits


19 Jul, 2018

12 commits