19 Oct, 2020
1 commit
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size_t used here are "long unsigned int", so use %lx when print it to
avoid the build warnings.Signed-off-by: Clark Wang
Reviewed-by: Fugang Duan
(cherry picked from commit 1fecb7888699f9b7c9c750c65091b2fdef1da3ac)
08 May, 2020
1 commit
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Conflicts:
drivers/spi/fsl_qspi.c
include/configs/mx6sxsabresd.h
include/configs/mx6ul_14x14_evk.h
include/configs/mx6ullevk.hAccording to the feedback from Priyanka and Ashish, the qspi framework has
big changes to port the existing Linux driver to replace the old qspi driver.
The patches has been accepted in the u-boot upstream and will be in 2020.07So, the suggestion is to override the imx_uboot conflicts, which means some
platform support is droppped such as the imx7ulp(not on the Linux upstream)
and some imx local patches need be reworked based on community new qspi driverThis need Li Ye and Han Xu to rework on the imx port
Signed-off-by: Jason Liu
06 May, 2020
18 commits
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iMX8MM DDR3L validation board uses GD25LQ16, but its id is not in
u-boot flash ids table. Add the new id and parameters into the table.Signed-off-by: Ye Li
(cherry picked from commit 04b813d4687028ce65c9772029d5da5500ec2e1c)
(cherry picked from commit 2257fe832100960b1cac96b92ecdd21d581bf33b) -
Add more BCH setting mode and remove the unnecessary platform constrain
Signed-off-by: Han Xu
(cherry picked from commit eb97412a839ce7a27267beee2dc0ab264d7fa131) -
the function named mxs_nand_ecc_read_page
To enable the Randomizer module, set GPMI_ECCCTRL[RANDOMIZER_ENABLE] to
1, then set GPMI_ECCCOUNT[RANDOMIZER_PAGE] to select randomizer page
number needed to be randomized.Signed-off-by: Alice Guo
(cherry picked from commit e8271a1c7621cc3607d3e9c7b0a872342b5f4c95) -
When enabled randomizer during ECC reading, the controller reported it's
erased page. Checking zero count will cause data get modified to all
0xFF. Stop checking during randomizer to workaround this issue.Signed-off-by: Han Xu
(cherry picked from commit f88f68f29026b084396db003c60e0c15995d1670) -
randomizer
imx8mm-evk needs to BCH encode and set NAND page number needed to be
randomizedmodify conditional compilation
Should use CONFIG_IMX8M, it should apply to imx8mq/mm/mn
Signed-off-by: Alice Guo
(cherry picked from commit da40cd99e4b3a78d2609ee777d60d651d6dbc313) -
gf_13/14 mask was not set correctly in register definition.
Signed-off-by: Han Xu
(cherry picked from commit b8aed98b2ecfb0def64c474e1ae171930da4c9fc) -
On mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters
and IDs to flash parameter array. Otherwise, the flash probe will fails.Signed-off-by: Ye Li
(cherry picked from commit 0d6bee19bb3e87ebf984fdc218b3b020006cb2e9)
(cherry picked from commit c711acf362985388fc53a0dbc4c6d81dc642168f) -
Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
(cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db)
(cherry picked from commit 99b54a6965904a879afdb6883a519de726cb4e96) -
add the dedicate compatible string for i.MX6QP
Signed-off-by: Han Xu
(cherry picked from commit 69a71623f1017705127afc94307d76afa1241519) -
The iMX6SX uses compatible string "fsl,imx6sx-gpmi-nand" for gpmi
node in DTS, so update the driver for the stringSigned-off-by: Ye Li
(cherry picked from commit e39d35e953390de6604f474866205b430f51fa2e) -
Update the mini driver to add support for getting ecc info from ONFI and
support read image data from page unaligned NAND address.Signed-off-by: Ye Li
(cherry picked from commit 45e34020f7b1e3996e99f24c5e18a08448fe1ca5) -
Since iMX8 has enabled clock uclass, we can parse the clocks from DTB
and enable them in GPMI driver.Signed-off-by: Ye Li
(cherry picked from commit 72cf8b976221913b7e36f8c53dc57a52206da26b) -
enable the GPMI NAND driver for i.MX8, the major changes
- register defination for i.mx8
- Makefile change for misc.c
- DMA structure must be 32bit addressSigned-off-by: Han Xu
(cherry picked from commit 474c4270108551647c7064a23abdc2e11d7f37ab)
(cherry picked from commit 029cce25cce94c30dd0305bb9b17ba7f939ee1af)
(cherry picked from commit a9f0815c22f5fecf4c4d2ac84cc39e62fe7998a2) -
Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M.
Signed-off-by: Ye Li
(cherry picked from commit 6cb839cabb42b81e37214e00448fc5dac89fd1f1)
(cherry picked from commit 468509f86a2d040398aa6b019bb6644bfb0ef11c)
(cherry picked from commit cac7f6b2408a8010ac411f562a635944e710626a) -
This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
Signed-off-by: Peng Fan
(cherry picked from commit 489929be0221bb7d4c46bb5bc6083650b78f73e0)
Signed-off-by: Ye Li
(cherry picked from commit 37d7f9614aa357f270312d7ceaab0f7006dc5aea)
(cherry picked from commit 5f50a850dd42d28b6105ee7e1b4b1822e7ba569b)
(cherry picked from commit 722f0ff0bcaec84c94c8fc211abdfbe457ea3dc6) -
This patch is porting from linux:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768"
We may meet the bitflips in reading an erased page(contains all 0xFF),
this may causes the UBIFS corrupt, please see the log from Elie:-----------------------------------------------------------------
[ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
...
[ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
[ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
[ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
-----------------------------------------------------------------This patch does a check for the uncorrectable failure in the following steps:
[0] set the threshold.
The threshold is set based on the truth:
"A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
do the ECC."For the sake of safe, we will set the threshold with half the gf_len, and
do not make it bigger the ECC strength.[1] count the bitflips of the current ECC chunk, assume it is N.
[2] if the (N
(cherry picked from commit ceb324a2914487aa517a6c70a06a20b5e3438fda)
(cherry picked from commit 026751697e41c7376414a8716cf0ea4bf998b85f)
(cherry picked from commit 93b481f07b8cb59c733f420bebea77ac484f9036)
(cherry picked from commit eefb30b8e68d522bd315ed884c36cb9b7e917f71) -
Provide an option in DT to use legacy bch geometry, which compatible
with the 3.10 kernel bch setting. To enable the feature, adding
"fsl,legacy-bch-geometry" under gpmi-nand node.NOTICE: The feature must be enabled/disabled in both u-boot and kernel.
Signed-off-by: Han Xu
Signed-off-by: Ye Li
(cherry picked from commit 71253252c6652a845df15d6288e49d37cdab3383) -
The code change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.Previous code has two methods for ECC layout setting, the
legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference
between these two methods is, legacy_calc_ecc_layout set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the calc_ecc_layout_by_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.2. If the oob is large or NAND required data chunk larger than oob size,
chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info3. legacy_calc_ecc_layout only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.Signed-off-by: Han Xu
Signed-off-by: Ye Li
(cherry picked from commit 71fe512f8fe173001a295399758d20a16a866a56)
01 May, 2020
1 commit
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Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on
various platforms as former is not present. Add the entry.Linux already has both the flashes present. A snippet below:
{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...},
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...},Signed-off-by: Kuldeep Singh
27 Apr, 2020
1 commit
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Commit 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support")
enables octal mode(1-1-8) support in spi-nor framework.mt35xu512aba and mt35xu02g supports SINGLE and OCTAL I/O. Hence, enable
SPI_NOR_OCTAL_READ flag for these flashes.Signed-off-by: Kuldeep Singh
Reviewed-by: Vignesh Raghavendra
03 Apr, 2020
1 commit
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Add Macronix MX25U3235F flash device description.
This is a 4MiB part.Signed-off-by: Tom Warren
28 Feb, 2020
1 commit
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Fixed wrong enumeration of nand_config structure. Added chip select
function before reading the nand chip for maf/dev id's, without this
unable to access id's from some of the micron chips. Also added a
print statement to identify if a nand flash is using on-die ecc.Signed-off-by: T Karthik Reddy
Signed-off-by: Michal Simek
19 Feb, 2020
2 commits
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The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.Factor them out to , and make all drivers to
include instead of .If we need to differentiate them for some architectures, we can
move the generic definitions to .Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.Signed-off-by: Masahiro Yamada
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dma_unmap_single() takes the dma address, not virtual address.
Signed-off-by: Masahiro Yamada
06 Feb, 2020
3 commits
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At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
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At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin -
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().Signed-off-by: Simon Glass
01 Feb, 2020
6 commits
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UCLASS_MTD is a better fit for NAND drivers.
Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile
drivers/mtd/mtd-uclass.cAlso, make ARCH_UNIPHIER select DM_MTD because all the defconfig
of this platform enables NAND_DENALI_DT.Signed-off-by: Masahiro Yamada
Reviewed-by: Miquel Raynal -
Currently, the denali NAND driver in U-Boot configures the
SPARE_AREA_SKIP_BYTES based on the CONFIG option.Recently, Linux kernel merged a patch that associates the proper
value for this register with the DT compatible string.Do likewise in U-Boot too.
The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES.
Signed-off-by: Masahiro Yamada
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When the reset signal is de-asserted, the HW-controlled bootstrap
starts running unless it is disabled in the SoC integration.
It issues some commands to detect a NAND chip, and sets up registers
automatically. Until this process finishes, software should avoid
any register access.Without this delay function, some of UniPhier boards hangs up while
executing nand_scan_ident(). (denali_read_byte() is blocked)Signed-off-by: Masahiro Yamada
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The Denali NAND driver in mainline Linux currently cannot deassert the
reset. The upcoming Linux 5.6 will support the reset controlling, and
also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in
the future kernel will work without relying on any bootloader or firmware.
However, we still need to take care of stable kernel versions for a while.
U-boot should not assert the reset of this controller.Fixes: ed784ac3822b ("mtd: rawnand: denali: add reset handling")
Signed-off-by: Marek Vasut
[yamada.masahiro: reword the commit description]
Signed-off-by: Masahiro Yamada -
The "nand_x" and "ecc" clocks are currently optional. Make the core
clock optional in the same way. This will allow platforms with no clock
driver support to use this driver.Signed-off-by: Masahiro Yamada
Tested-by: Marek Vasut # On SoCFPGA Arria V -
On Altera SoCFPGA, upon either cold-boot or power-on reset, the
Denali NAND IP is initialized by the BootROM ; upon warm-reset,
the Denali NAND IP is NOT initialized by BootROM. In fact, upon
warm-reset, the SoCFPGA BootROM checks whether the SPL image in
on-chip RAM is valid and if so, completely skips re-loading the
SPL from the boot media.This does sometimes lead to problems where the software left
the boot media in inconsistent state before warm-reset, and
because the BootROM does not reset the boot media, the boot
media is left in this inconsistent state, often until another
component attempts to access the boot media and fails with an
difficult to debug failure. To mitigate this problem, the SPL
on Altera SoCFPGA always resets all the IPs on the SoC early
on boot.This results in a couple of register values, pre-programmed by
the BootROM, to be lost during this reset. To restore correct
operation of the IP on SoCFPGA, these values must be programmed
back into the controller by the driver. Note that on other SoCs
which do not use the HW-controlled bootstrap, more registers
may have to be programmed.This also aligns the SPL behavior with the full Denali NAND
driver, which sets these values in denali_hw_init().Signed-off-by: Marek Vasut
Signed-off-by: Masahiro Yamada
28 Jan, 2020
2 commits
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Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.Signed-off-by: Vignesh Raghavendra
Reviewed-by: Jagan Teki -
Linux has supported W25N01GV for a long time, so lets import it.
Signed-off-by: Robert Marko
Cc: Luka Perkov
Reviewed-by: Jagan Teki
26 Jan, 2020
1 commit
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Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementationSigned-off-by: Vignesh Raghavendra
Acked-by: Masahiro Yamada
23 Jan, 2020
1 commit
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This adds the nand support for chipset bcm68360.
Signed-off-by: Philippe Reynes
18 Jan, 2020
1 commit
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At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.Signed-off-by: Simon Glass
[trini: Migrate a few more files]
Signed-off-by: Tom Rini