05 Mar, 2018
1 commit
-
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.hand replaces include directives:
#include -> #include
#include -> #includeReported-by: Thomas Petazzoni
Signed-off-by: Masahiro Yamada
19 Feb, 2018
1 commit
-
Only ARM and in some configs MIPS really implement arch_fixup_fdt().
Others just use the same boilerplate which is not good by itself,
but what's worse if we try to build with disabled CONFIG_CMD_BOOTM
and enabled CONFIG_OF_LIBFDT we'll hit an unknown symbol which was
apparently implemented in arch/xxx/lib/bootm.c.Now with weak arch_fixup_fdt() right in image-fdt.c where it is
used we get both items highlighted above fixed.Signed-off-by: Alexey Brodkin
Cc: Daniel Schwierzeck
Cc: Simon Glass
Cc: York Sun
Cc: Stefan Roese
Reviewed-by: Tom Rini
Reviewed-by: Daniel Schwierzeck
30 Jan, 2018
6 commits
-
The variable t_rfc is never used, so drop it. The variables ddr_wctl
and ddr_wcmd are only used in certain manual instances, so guard their
declaration by the same check as their use.Cc: Bin Meng
Signed-off-by: Tom Rini
Reviewed-by: Bin Meng
Tested-by: Bin Meng -
At present the acpi_rsdp_addr variable is directly referenced in
setup_zimage(). This changes to use an API for better encapsulation
and extension.Signed-off-by: Bin Meng
Reviewed-by: Andy Shevchenko -
New field acpi_rsdp_addr, which has been introduced in boot protocol
v2.14 [1], in boot parameters tells kernel the exact address of RDSP
ACPI table. Knowing it increases robustness of the kernel by avoiding
in some cases traversal through a part of physical memory.
It will slightly reduce boot time by the same reason.[1] See Linux kernel commit
2f74cbf ("x86/boot: Add the ACPI RSDP address to struct setup_header::acpi_rdsp_addr")
@ https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=2f74cbffor the details.
Signed-off-by: Andy Shevchenko
Reviewed-by: Bin Meng
[bmeng: updated the kernel commit git URL and fixed one style issue]
Signed-off-by: Bin Meng -
The commit
20bfac0599bd ("x86: zImage: add Intel MID platforms support")
introduced an assignment of subarch field in boot parameters, though
missed the right place of doing that. It doesn't matter if we have or
not a kernel command line supplied, we just set that field. Although
guard it by protocol version which supports it.Fixes: 20bfac0599bd ("x86: zImage: add Intel MID platforms support")
Cc: Vincent Tinelli
Signed-off-by: Andy Shevchenko
Reviewed-by: Bin Meng -
The commit
eece493a7ac1 ("cmd: qfw: bring ACPI generation code into qfw core")
moves ACPI related code to another file and missed an update of
references in acpi_table.c.Do it now.
Fixes: eece493a7ac1 ("cmd: qfw: bring ACPI generation code into qfw core")
Cc: Miao Yan
Signed-off-by: Andy Shevchenko
Reviewed-by: Bin Meng -
ASL compiler warns:
ASL board/intel/edison/dsdt.asl
board/intel/edison/dsdt.asl.tmp 238: Method (_CRS, 0, NotSerialized)
Remark 2120 - Control Method should be made Serialized ^ (due to creation of named objects within)Do as suggested by ASL compiler.
Fixes: 5d8c4ebd95e2 ("x86: tangier: Add Bluetooth to ACPI table")
Reported-by: Ferry Toth
Signed-off-by: Andy Shevchenko
Reviewed-by: Bin Meng
08 Jan, 2018
3 commits
-
As defined on reference board followed by Intel Edison a Bluetooth
device is attached to HSU0, i.e. PCI 0000:04.1.Describe it in ACPI accordingly.
Note, we use BCM2E95 ID here as one most suitable for such device based
on the description in commit message of commit 89ab37b489d1
("Bluetooth: hci_bcm: Add support for BCM2E95 and BCM2E96")
in the Linux kernel source tree.Signed-off-by: Andy Shevchenko
Acked-by: Bin Meng
Reviewed-by: Simon Glass -
The recent commit 03c4749dd6c7
("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation")
in the Linux kernel reveals the issue we have in ACPI tables here,
i.e. we must use hardware numbers for GPIO resources and,
taking into consideration that GPIO and pin control are *different* IPs
on Intel Tangier, we need to supply numbers properly.Besides that, it improves user experience since the official documentation
for Intel Edison board is referring to GPIO hardware numbering scheme.Signed-off-by: Andy Shevchenko
Acked-by: Bin Meng
Reviewed-by: Simon Glass -
We only need to compile and link these files when building for full
U-Boot. Move them to under cmd/x86/ to make sure they aren't linked in
and undiscarded due to u_boot_list_2_cmd_* being included).Cc: Bin Meng
Signed-off-by: Tom Rini
Reviewed-by: Bin Meng
21 Dec, 2017
1 commit
-
FLIS IP since now gets its own ACPI ID.
Drop PRP0001 workaround in favour of official ACPI HID.Corresponding kernel commit dabd4bc6de2b
pinctrl: intel: merrifield: Introduce ACPI device table
in the pin control subsystem tree [1] targeting v4.16.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=dabd4bc6de2b
Reviewed-by: Bin Meng
Signed-off-by: Andy Shevchenko
13 Dec, 2017
1 commit
-
And use 'imply' liberally.
Signed-off-by: Tuomas Tynkkynen
30 Nov, 2017
4 commits
-
This patch removes the inclusion of the libgcc math functions and
replaces them by functions coded in C, taken from the coreboot
project. This makes U-Boot building more independent from the toolchain
installed / available on the build system.The code taken from coreboot is authored from Vadim Bendebury
on 2014-11-28 and committed with commit
ID e63990ef [libpayload: provide basic 64bit division implementation]
(coreboot git repository located here [1]).I modified the code so that its checkpatch clean without any
functional changes.[1] git://github.com/coreboot/coreboot.git
Signed-off-by: Stefan Roese
Cc: Simon Glass
Cc: Bin Meng
Reviewed-by: Bin Meng
Tested-by: Bin Meng -
This reverts commit 13c531e52a09b4e6ffa8b5a1457199b0a574cb27.
The error message with FIT style image mentioned in the above commit
only happens when booting using FIT image containing bzImage kernel
and without setup node (setup.bin). The current documentation for
x86 FIT support in doc/uImage.FIT/x86-fit-boot.txt mentions that
kernel's setup.bin file is required for building x86 FIT images.
The above commit breaks FIT images generated as described in the
documentation. Revert it to allow booting with images built in the
documented way.Signed-off-by: Anatolij Gustschin
Reviewed-by: Stefan Roese
Acked-by: Bin Meng -
x86_vendor_name is defined as
static const char *const x86_vendor_name[]
So its elements should not be compared to 0.
Remove superfluous paranthesis.
Problem identified with Coccinelle.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Bin Meng -
ROM has been made read-only in qemu recently (namely commit 208fa0e4:
"pc: make 'pc.rom' readonly when machine has PCI enabled"). So this
patch restores compatibility between U-Boot and qemu.Signed-off-by: Anton Gerasimov
Reviewed-by: Bin Meng
Tested-by: Bin Meng
[bmeng: mention qemu commit title in the commit message]
Signed-off-by: Bin Meng
17 Nov, 2017
1 commit
-
Currently, pylibfdt is always compiled if swig is installed on your
machine. It is really annoying because most of targets (excepts
x86, sunxi, rockchip) do not use dtoc or binman."checkbinman" and "checkdtoc" are wrong. It is odd that the final
build stage checks if we have built necessary tools. If your platform
depends on dtoc/binman, you must be able to build pylibfdt. If swig
is not installed, it should fail immediately.I added PYLIBFDT, DTOC, BINMAN entries to Kconfig. They should be
property select:ed by platforms that need them. Kbuild will descend
into scripts/dtc/pylibfdt/ only when CONFIG_PYLIBFDT is enabled.Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
27 Oct, 2017
7 commits
-
The supported sleep states are generic on Intel processors. Move the
ASL definition to the common place.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
On some platforms (eg: Braswell), the FSP will not produce the
graphics info HOB unless you plug some cables to the display
interface (eg: HDMI) on the board. Add such notes in the FSP
video driver.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Intel Braswell FSP requires SPI controller settings to be locked down,
let's do this in the chrryhill.dts and remove previous Kconfig option.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
This reverts commit 1e6ebee667da47fd3a87839a239a7574c66f5659.
It's not appropriate to call the Intel SPI driver specific stuff in
the FSP codes. We may add a simple DTS property "intel,spi-lock-down"
and let the Intel SPI driver call these stuff instead.Signed-off-by: Bin Meng
-
In an S3 resume path, MRC cache is mandatory. Enforce the dependency
in the Kconfig.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Imply does not work for a Kconfig choice. Update ENV_IS_IN_SPI_FLASH
to be the default one for Intel Braswell.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes kernel
just oops, while sometimes kernel throws MCE errors and hangs:mce: [Hardware Error]: Machine check events logged
mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151
mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0
mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363This looks like a hardware error per mcelog. After debugging, it
seems turning off turbo mode on the processor does not expose this
behavior, although U-Boot runs OK with turbo mode on. Suspect it is
related to an errata of Braswell processor.To fix this, remove the Braswell cpu driver which does the turbo
mode configuration, and switch to use the generic cpu-x86 driver.
Also there is a configuration option in the FSP that turns on the
turbo mode and that has been turned off too.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
19 Oct, 2017
5 commits
-
Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.Signed-off-by: Bin Meng
Reviewed-by: Stefan Roese -
At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.Signed-off-by: Bin Meng
Reviewed-by: Stefan Roese -
So far there are two copies of Azalia struct defines with one in
baytrail and the other one in braswell. This consolidates these
two into one, put it in the common place, and remove the prefix
pch_ to these structs to make their names more generic.This also corrects reset_wait_timer from us to ms.
Signed-off-by: Bin Meng
Reviewed-by: Stefan Roese -
This is only needed when graphics console is used. For kernel with
native graphics driver, this can be turned off to speed up.Change this option's default to n in the Kconfig.
Signed-off-by: Bin Meng
Reviewed-by: Stefan Roese -
It was observed that when booting a Ubuntu 16.04 kernel, doing ACPI
S3 suspend/resume sometimes causes the Ubuntu kernel hang forever.
The issue is however not reproduced with a kernel built from i386/
x86_64 defconfig configuration.The unstability is actually caused by unexpected interrupts being
generated during the S3 resume. For some unknown reason, FSP (gold4)
for BayTrail configures the GPIO DFX5 PAD to enable level interrupt
(bit 24 and 25). As this pin keeps generating interrupts during an
S3 resume, and there is no IRQ requester in the kernel to handle it,
the kernel seems to hang and does not continue resuming.Clear the mysterious interrupt bits for this pin.
Reported-by: Stefan Roese
Signed-off-by: Bin Meng
Tested-by: Stefan Roese
Reviewed-by: Stefan Roese
07 Oct, 2017
1 commit
-
Intel Tangier SoC is a part of Intel Merrifield platform which doesn't
utilize ACPI by default. Here is an attempt to unleash ACPI flexibility
power on Intel Merrifield based platforms.The change brings minimum support of the devices that found on
Intel Merrifield based end user device.Signed-off-by: Andy Shevchenko
Reviewed-by: Bin Meng
04 Oct, 2017
1 commit
-
U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
//
@@@@
-error
+pr_err
(...)
//Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini
03 Oct, 2017
1 commit
-
Convert the x86 architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for x86 this is primarily a matter of moving code.This has only been build-tested, feedback from architecture maintainers
is welcome.Signed-off-by: Paul Burton
Cc: Simon Glass
Reviewed-by: Simon Glass
16 Sep, 2017
7 commits
-
legacy_hole_base_k and legacy_hole_size_k are defined but
not used.Signed-off-by: Heinrich Schuchardt
Reviewed-by: Simon Glass
Reviewed-by: Bin Meng -
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.This will be used by the 'early' timer also.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video consoleSigned-off-by: Bin Meng
Reviewed-by: Simon Glass -
FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
Add FSP related configuration for Braswell.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
