29 Jul, 2006

1 commit

• a2c95a722   PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance ... Browse Code »

  AMCC suggested to set the PMU bit to 0 for best performace on
  the PPC440 DDR controller.
  Please see doc/README.440-DDR-performance for details.
  Patch by Stefan Roese, 28 Jul 2006

  Stefan Roese

  2006-07-29 00:34:58 +0800