21 Oct, 2015
11 commits
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On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V, make this
the default.Note that this does not cause any functional changes since all sun8i
board defconfig-s already contained: CONFIG_AXP_ALDO1_VOLT=3000 .Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
Change the axp223 dcdc2 / VDD-SYS default from 1.2V to 1.1V, 1.1V is the
value recommended by Allwinner and is what most fex files specify.This has been tested on a number of A23/A33 tablets including on an
A23 Ippo-q8h-v1.2 PCB tablet which has a fex file which specifies 1.2V
(which is where our original 1.2V default comes from).Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
Stop prefixing the axp functions for setting voltages, etc. with the
model number, there ever is only one pmic driver built into u-boot,
this allows simplifying the callers.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
On boards with axp221/223 pmic-s we already allow configuring most
voltages. Make the Kconfig options for these also apply to boards with
axp152 / axp209 pmic-s and extend them to configure all voltages.The Kconfig defaults are chosen so that this commit does not introduce any
functional changes.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
Kconfig-ify CONFIG_AXP152_POWER and _AXP209_POWER settings, removing
them from CONFIG_SYS_EXTRA_OPTIONS.Note that sun5i boards can have either an AXP209 or an AXP152 pmic, the
Kconfig default is AXP209, boards with an AXP152 must explicitly select
this. Likewise boards without a pmic must explicitly select SUNXI_NO_PMIC
in their defconfig.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
We now have generic q8_a?3_defconfig files for Q8 formfactor tablets with
an A13 / A23 / A33 SoC, there is no need for these PCB variant specific
defconfig-s and they only serve to confuse the user.Note that in case of the forfun_q88db_defconfig and TZX-Q8-713B7_defconfig
for A13 based Q8 tablets there is not even a dts file for these in the
upstream kernel, which is all the more reason to remove them.The generic q8_a?3_defconfig files have been tested on an Et_q8_v1_6,
Ippo_q8h_v1_2_a33_1024x600, Ippo_q8h_v1_2 and TZX-Q8-713B7 tablet, and the
forfun_q88db_defconfig is identical to q8_a13_tablet_defconfig.This leaves only the Ippo_q8h_v5 untested with the new generic defconfigs
but there is no reason to assume that it will not work.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a
Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes,
and .data from 0x54c to 0x144 bytes.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
Reviewed-by: Tom Rini -
Select CONFIG_SPL_STACK_R for sunxi boards, this gives us much more
room on the stack once we've the DRAM running.Besides being a good change to have on itself, this also paves the
way for switching to using malloc_simple in the SPL which cuts of
close to 4KiB of the SPL size.Signed-off-by: Hans de Goede
Reviewed-by: Tom Rini -
malloc_simple uses a part of the stack as heap, initially it uses
SYS_MALLOC_F_LEN bytes which typically is quite small as the initial
stacks sits in SRAM and we do not have that much SRAM to work with.When DRAM becomes available we may switch the stack from SRAM to DRAM
to give use more room. This commit adds support for also switching to
a new bigger malloc_simple heap located in the new stack.Note that this requires spl_init to be called before spl_relocate_stack_gd
which in practice means that spl_init must be called from board_init_f.Signed-off-by: Hans de Goede
Reviewed-by: Tom Rini
Acked-by: Simon Glass -
common/dlmalloc.c is quite big, both in .text and .data usage, therefor
on some boards the SPL is build to use only malloc_simple.c and not the
dlmalloc.c code. This is done in various include/configs/foo.h with the
following construct:#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endifThis commit introduces a SPL_MALLOC_SIMPLE Kconfig bool which allows
selecting this functionality through Kconfig instead.Signed-off-by: Hans de Goede
Acked-by: Simon Glass -
spl_relocate_stack_gd only gets called from arch/arm/lib/crt0.S which
clears the bss directly after calling it, so there is no need to clear
it from spl_relocate_stack_gd.Signed-off-by: Hans de Goede
Reviewed-by: Simon Glass
20 Oct, 2015
16 commits
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Signed-off-by: Tom Rini
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This code is no-longer used. Drop it.
Signed-off-by: Simon Glass
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Signed-off-by: Paul Gortmaker
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Between v2015.07-rc1 and v2015.07-rc2 this board started
silent boot failure. A bisect led to commit 6eed3786c68c8a49d
("net: Move the CMD_NET config to defconfigs"). This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:u-boot$git describe 6eed3786c68c8a49d
v2015.07-rc1-412-g6eed3786c68c
^^^u-boot$ls -l ../41*/u-boot.bin
-rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
-rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
u-boot$bc
bc 1.06.95
Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc.
This is free software with ABSOLUTELY NO WARRANTY.
For details type `warranty'.
256*1024
262144i.e. we finally broke through the 256k monitor size. Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.Signed-off-by: Paul Gortmaker
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...so that I don't have to go work them out from scratch again
by peering at the manual.Signed-off-by: Paul Gortmaker
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When debugging an env fail due to too small a malloc pool, it
was noted that the env write was 256k. But the device sector
size is 1/2 that, as can be seen from "fli" output:Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 131 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1888
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 2 ms, buffer size: 64 bytesSector Start Addresses:
FF000000 E RO FF020000 E RO FF040000 E RO FF060000 E RO FF080000 E RO
FF0A0000 E RO FF0C0000 E RO FF0E0000 E RO FF100000 E RO FF120000 E RO
[...]
FFF00000 RO FFF20000 RO FFF40000 RO FFF60000 RO FFF80000 RO
FFFA0000 RO FFFC0000 RO FFFE0000 E RO FFFE8000 RO FFFF0000 E RO
FFFF8000 RO
=>The desired env sector is FFF40000->FFF60000, or 0x20000 in length,
just after the 256k u-boot image which starts @ FFF00000.Signed-off-by: Paul Gortmaker
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Currently the board fails to save its env, since the env size
is much smaller than the sector size, and the malloc fails for
the pad buffer, giving the user visible symptom of:Unable to save the rest of sector (253952)
Allow for 1M malloc pool, the same as used on the sbc8548 board.
Signed-off-by: Paul Gortmaker
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It is just too painful to use interactively without it.
Signed-off-by: Paul Gortmaker
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On signature verification failures fit_image_verify() should
exit with error.Signed-off-by: Andrej Rosano
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Used NAND chips requires at least 4-bit error correction, so use BCH8
as it is what kernel uses.Signed-off-by: Ladislav Michl
Acked-by: Javier Martinez Canillas -
Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.Signed-off-by: Liviu Dudau
Tested-by: Ryan Harkin
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: Tom Rini -
Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.Signed-off-by: Liviu Dudau
Reviewed-by: Linus Walleij
Reviewed-by: Ryan Harkin
Tested-by: Ryan Harkin -
The dfu_alt_info_spl variable allows passing a starting point
for the binary to be flashed in the SPI NOR.For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means
that we want to flash the binary starting at address 0x400.In order to do so we need to erase the entire sector and write to
the the subsequent SPI NOR sectors taking such start address
into account for the address calculations.Tested by succesfully writing SPL binary into 0x400 offset and
the u-boot.img at offset 64 kiB of a SPL NOR.Signed-off-by: Fabio Estevam
Acked-by: Lukasz Majewski
[trini: Use lldiv for the math]
Signed-off-by: Tom Rini -
SPI NOR flashes need to erase the entire sector size and we cannot pass
any arbitrary length for the erase operation.To illustrate the problem:
Copying data from PC to DFU device
Download [=========================] 100% 478208 bytes
Download done.
state(7) = dfuMANIFEST, status(0) = No error condition is present
state(10) = dfuERROR, status(14) = Something went wrong, but the
device does not know what it was
Done!In this case, the binary has 478208 bytes and the M25P32 SPI NOR
has an erase sector of 64kB.478208 = 7 entire sectors of 64kiB + 19456 bytes.
Erasing the first seven 64 kB sectors works fine, but when trying
to erase the remainding 19456 causes problem and the board hangs.Fix the issue by always erasing with the erase sector size.
Signed-off-by: Fabio Estevam
Acked-by: Lukasz Majewski -
- Add deletions from August 30 2015.
- A few from Sept 12, one from Oct 2nd.Signed-off-by: Tom Rini
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Upon further review when populating README.scrapyard, inetspace_v2_cmc
is a variant on netspace_v2 and not just an orphan config.This reverts commit 653600a715db49859c06ba5dfb858c15c4108d54.
Signed-off-by: Tom Rini
19 Oct, 2015
5 commits
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Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config. To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.This reverts commit 1363740e7948a8e4bee8d5adcdf0f63f7782879d.
Cc: Simon Guinot
Cc: Simon Glass
Signed-off-by: Tom Rini -
Add in the commit IDs / dates for boards removed on Sept 2nd.
Signed-off-by: Tom Rini
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Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.Signed-off-by: Lubomir Rintel
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The default dockstar configuration for U-Boot currently causes it to
overrun the environment area, so that a "saveenv" command bricks the
device. This patch moves the environment to a higher address to avoid
that.Signed-off-by: Eric Cooper
18 Oct, 2015
1 commit
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On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov "
and based on the previous work done by "Hao Zhang "Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov
Tested-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla
17 Oct, 2015
4 commits
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There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.Tested-by: Joakim Tjernlund
Signed-off-by: Tom Rini -
We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.Signed-off-by: Dinh Nguyen
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Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.Signed-off-by: Dinh Nguyen
16 Oct, 2015
3 commits
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This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).Signed-off-by: Anthony Felice
Reviewed-by: Fabio Estevam -
Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163)
Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU and later causes a PCIE VA access
failure.Signed-off-by: Alison Wang
