16 Aug, 2016

1 commit

• de5e5cea0   xtensa: add support for the xtensa processor architecture [1/2] ... Browse Code »

  The Xtensa processor architecture is a configurable, extensible,
  and synthesizable 32-bit RISC processor core provided by Cadence.

  This is the first part of the basic architecture port with changes to
  common files. The 'arch/xtensa' directory, and boards and additional
  drivers will be in separate commits.

  Signed-off-by: Chris Zankel
  Signed-off-by: Max Filippov
  Reviewed-by: Simon Glass
  Reviewed-by: Tom Rini

  Chris Zankel

  2016-08-16 06:46:38 +0800