28 Aug, 2017

1 commit

  • So far cache operations are only applied on the submission queue and
    completion queue, but they are missing in other places like identify
    and block read/write routines.

    In order to correctly operate on the caches, the DMA buffer passed
    to identify routine must be allocated properly on the stack with the
    existing macro ALLOC_CACHE_ALIGN_BUFFER().

    Signed-off-by: Bin Meng

    Bin Meng
     

14 Aug, 2017

1 commit