14 Oct, 2016
1 commit
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cpsw driver supports only selection of phy mode in control module
but control module has more setting like RGMII ID mode selection,
RMII clock source selection. So ported to cpsw-phy-sel driver
from kernel to u-boot.Signed-off-by: Mugunthan V N
Signed-off-by: Lokesh Vutla
Acked-by: Joe Hershberger
25 May, 2016
2 commits
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Add the ability to read the phy-handle node of the
cpsw slave. Upon reading this handle the phy-id
can be stored based on the reg node in the DT.The phy-handle also needs to be stored and passed
to the phy to access any phy data that is available.Signed-off-by: Dan Murphy
Tested-by: Mugunthan V N
Acked-by: Joe Hershberger -
Different TI platforms has to read with different combination to
get the mac address from efuse. So add support to read mac address
based on machine/device compatibles.The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c
done by Tony Lindgren.Signed-off-by: Mugunthan V N
Reviewed-by: Tom Rini
Acked-by: Joe Hershberger
23 Oct, 2015
1 commit
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adopt cpsw driver to device driver model
Signed-off-by: Mugunthan V N
Reviewed-by: Simon Glass
26 Jul, 2014
1 commit
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Add support for using the second slave port of cpsw
to be used as primary ethernet.Signed-off-by: Mugunthan V N
04 Mar, 2014
1 commit
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Some platforms like AM437x have different EVMs with different phy addresses,
so this patch adds support for passing phy address via cpsw plaform data.
Also renamed phy_id to phy_addr so better understanding of the code.Reviewed-by: Felipe Balbi
Signed-off-by: Mugunthan V N
[trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335
pengwyn boards]
Signed-off-by: Tom Rini
27 Jul, 2013
1 commit
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BD ram address may vary in various SOC, so removing the hardcoding and
passing the same information through platform dataSigned-off-by: Mugunthan V N
01 Sep, 2012
1 commit
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CPSW is an on-chip ethernet switch that is found on various SoCs from Texas
Instruments. This patch adds a simple driver (based on the Linux driver) for
this hardware module.This patch also adds support to clean and flush dcache during packet send
and receive.Changes by Sandhya: Added support to clean and flush dcache during packet
send/receive and added timeouts.Signed-off-by: Cyril Chemparathy
Signed-off-by: Chandan Nath
Signed-off-by: Satyanarayana, Sandhya
[Ilya: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors]
Signed-off-by: Ilya Yanok