28 Jan, 2018
1 commit
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Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs.
The PCIe on Gen2 is used both to connect external PCIe peripherals as
well as access the on-SoC USB EHCI controller.Signed-off-by: Marek Vasut
06 Oct, 2017
1 commit
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QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
The 'highmem=off' part is required for things to work as the PCI code
in U-Boot doesn't seem to support 64-bit BARs.Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Bin Meng
22 Sep, 2017
1 commit
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'default n' is the default anyway so it doesn't need to be specified
explicitly, and the rest of the file doesn't specify it either anywhere.
Drop it.Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Bin Meng
01 Aug, 2017
1 commit
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PCI is the de facto interconnect bus in an x86 system.
Signed-off-by: Bin Meng
Reviewed-by: Andy Shevchenko
Reviewed-by: Simon Glass
19 Jan, 2017
1 commit
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There are more than five kinds of Layerscape SoCs. unfortunately,
PCIe controller of each SoC is a little bit different. In order
to avoid too many macro definitions, the patch addes a new
implementation of PCIe driver based on DM. PCIe dts node is
used to describe the difference.Signed-off-by: Minghuan Lian
Signed-off-by: Hou Zhiqiang
Reviewed-by: Simon Glass
Reviewed-by: York Sun
04 Jan, 2017
1 commit
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Fix 'driver model' rather than 'driver mode' in description.
Signed-off-by: Marcel Ziswiler
Signed-off-by: Tom Warren
05 Dec, 2016
1 commit
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This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.Tested on the Marvell DB-88F8040 Armada-8K eval board.
Signed-off-by: Shadi Ammouri
Signed-off-by: Yehuda Yitschak
Signed-off-by: Stefan Roese
Reviewed-by: Simon Glass
Cc: Nadav Haklai
Cc: Neta Zur Hershkovits
Cc: Kostya Porotchkin
Cc: Omri Itach
Cc: Igal Liberman
Cc: Haim Boot
Cc: Hanna Hawa
28 Oct, 2016
2 commits
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Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig
to use that.Signed-off-by: Bin Meng
Reviewed-by: Tom Rini
[trini: Re-generate configs and include/configs/ changes]
Signed-off-by: Tom Rini -
Add 'PCI' as a menu option and migrate all existing users.
Signed-off-by: Tom Rini
Acked-by: Stephen Warren
21 Sep, 2016
1 commit
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This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.Signed-off-by: Paul Burton
Reviewed-by: Simon Glass
16 Aug, 2016
1 commit
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Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.Signed-off-by: Stephen Warren
Reviewed-by: Simon Glass
Signed-off-by: Tom Warren
01 Dec, 2015
2 commits
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We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Move this option to Kconfig and fix up all users.
Signed-off-by: Simon Glass
Tested-by: Stephen Warren
17 Apr, 2015
2 commits
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Add a driver which can access emulations of devices and make them available
in sandbox.Signed-off-by: Simon Glass
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Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.TODO: Add more header file comments to the new parts of pci.h
Signed-off-by: Simon Glass
25 Sep, 2014
1 commit
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This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Tested-by: Simon Glass
