10 Jan, 2013
5 commits
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Report the usage of the Advanced Sector Protection (PPB) to the user
upon 'flinfo' command. E.g:Bank # 1: CFI conformant flash (16 x 16) Size: 64 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2301
Advanced Sector Protection (PPB) enabled
Erase timeout: 16384 ms, write timeout: 2 ms
Buffer write timeout: 5 ms, buffer size: 32 bytesSector Start Addresses:
FC000000 E FC020000 E RO FC040000 E FC060000 E FC080000 E
...Signed-off-by: Stefan Roese
Cc: Anatolij Gustschin
Cc: Holger Brunck
Tested-by: Holger Brunck -
Not only Spansion supports the Persistent Protection Bits (PPB) locking.
Other devices like the Micron JS28F512M29EWx also support this type
of locking/unlocking. Detection of support is done in the same way as
done for the Spansion chips - via the 0x49 CFI word.This patch enables this PPB protection mechanism for all AMD type
(AMD commandset) chips.Signed-off-by: Stefan Roese
Cc: Anatolij Gustschin
Cc: Holger Brunck
Tested-by: Holger Brunck -
Patch 66863b05 [cfi_flash: add support for Spansion flash PPB sector
protection] introduced the PPB (Persistent Protection Bit) locking for
Spansion chips. But right now the sector protection status (locked vs
unlocked) is set to unlocked for all sectors upon bootup. The real
sector protection status is ignored.This patch now reads the current sector protection status and uses
it for these AMD/Spansion flash chips.Signed-off-by: Stefan Roese
Cc: Anatolij Gustschin
Cc: Holger Brunck
Tested-by: Holger Brunck -
Consolidate manufacturer matching into the function manufact_match()
and use it.Signed-off-by: Stefan Roese
Tested-by: Holger Brunck -
Add support for SST 4KB sector granularity.
Many recent SST flashes, i.e. SST39VF3201B and similar of this family
are declared CFI-conformant from SST. They support CFI query, but implement
2 different sector sizes in the same memory: a 64KB sector (they call it
"block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector",
erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh
of cfi query struct, detects a number of secotrs for the 4KB granularity
(flinfo shows it).For all other aspects, they are CFI compliant, so, as Linux do, i think
it's a good idea to handle these chips in the CFI driver, with a fixup
to allow 4KB granularity, as should be expected, instead of 64KB.Signed-off-by: Angelo Dureghello
Signed-off-by: Stefan Rose
09 Jan, 2013
2 commits
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Signed-off-by: Albert ARIBAUD
08 Jan, 2013
2 commits
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This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
06 Jan, 2013
1 commit
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All esdhc variants we know should support high capacity MMC cards,
so let's add MMC_MODE_HC host_caps unconditionally to support those
MMC cards (capacity > 2 GB).Signed-off-by: Shawn Guo
22 Dec, 2012
4 commits
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This commit merges branches from samsung, imx and tegra
meant to fix merge issues between u-boot/master and
u-boot-arm/master, as well as a few manual merge fixes. -
IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Hemant Nautiyal
20 Dec, 2012
2 commits
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Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
Conflicts:
README
arch/arm/cpu/armv7/exynos/clock.c
board/samsung/universal_c210/universal.c
drivers/misc/Makefile
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/seaboard.h
18 Dec, 2012
1 commit
17 Dec, 2012
3 commits
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Well, not terminating the list causes very interesting crashes.
As in changing the vendor & product ID crashes. Fun.Signed-off-by: Pantelis Antoniou
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Call usb_gadget_connect/usb_gadget_disconnect in g_dnl_bind/g_dnl_unbind.
Signed-off-by: Pantelis Antoniou
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usbdescriptors.h conflicts with linux/usb/ch9.h.
Remove it.Signed-off-by: Lukasz Dalek
16 Dec, 2012
3 commits
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SH7752 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.Signed-off-by: Yoshihiro Shimoda
Acked-by: Nobuhiro Iwamatsu -
Marvell 88E1118R has different uid then 88E1118.
Signed-off-by: Michal Simek
CC: Andy Fleming
CC: Zang Roy-R61911
CC: Kumar Gala -
In e1000e driver, Rx descriptor queue is used such that hardware can add only
one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set
to single descriptor. This would ensure that every time controller fills a Rx
descriptor, it is flushed to host memory. Earlier this granularity was in
cache line units i.e 2 descriptors. This leads to controller always waiting
for 2 descriptors before flushing them out. But since not more than one Rx BD
is actually available , the accumulation condition never gets hit.Signed-off-by: Ruchika Gupta
Signed-off-by: Vakul Garg
Acked-by: Roy Zang
15 Dec, 2012
1 commit
14 Dec, 2012
1 commit
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Remove the hard-coded baudrate handler and use a callback instead
Signed-off-by: Joe Hershberger
12 Dec, 2012
15 commits
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It could happen (1 out of 100 times) that NAND did not start up correctly after
warm rebooting, so we end up with various failures or DMA timed out due to a
stalled BCH. When resetting BCH together with GPMI, the issue could not be
observed anymore (after 10000+ reboots). We probably need the consistent state
already before sending commands to NAND. This behaviour was observed in barebox
and kernel, so I assume it affects U-Boot as well. I chose to keep the extra
reset for BCH when changing the flash layout to be on the safe side.Signed-off-by: Wolfram Sang
Acked-by: Marek Vasut -
Signed-off-by: Armando Visconti
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Signed-off-by: Armando Visconti
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There are three couple (hcnt/lcnt) of registers for each
speed (SS/FS/HS). The driver needs to set the proper couple
of regs according to what speed we are setting.Signed-off-by: Armando Visconti
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In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.Signed-off-by: Armando Visconti
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This patch adds the capability to switch between 10
different I2C busses (from 0 to 9).Signed-off-by: Armando Visconti
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This patch modifies the S3C i2c driver to support both Exynos4 and Exynos5
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
CC: Minkyu Kang -
OMAP5 has 8b i2c data register field, like OMAP2, 3 and 4. Handle in the same
way. This fixes the following error on OMAP5:OMAP5430 EVM # mmc rescan
timed out in wait_for_bb: I2C_STAT=1410
twl6035: could not turn on LDO9.Signed-off-by: Vincent Stehlé
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This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.Signed-off-by: Marek Vasut
Cc: Stefano Babic
Cc: Fabio Estevam
Cc: Wolfgang Denk -
The I2C block reset configures the I2C bus speed to strange value.
Read the I2C speed from the block before reseting the block and
restore it afterwards, so the I2C operates correctly. This issue
can be replicated by doing unsuccessful I2C transfer, after such
transfer finishes, the I2C block clock speed is misconfigured.Signed-off-by: Marek Vasut
Cc: Heiko Schocher
Cc: Fabio Estevam -
According to FSL, the value in the TIMING2 register shall be 0x00300030
instead of what's written in the datasheet. This new value correlates
with older STMP36xx datasheet. Issues were detected in Linux when this
register was misconfigured, so write this correct value.Signed-off-by: Marek Vasut
Cc: Stefano Babic
Cc: Fabio Estevam -
Use i2c_set_bus_speed() in i2c_init() within the mxs i2c driver
to avoid duplication of code.Signed-off-by: Marek Vasut
Cc: Stefano Babic
Cc: Fabio Estevam -
This patch implements the setup and retrieval functions for the I2C
bus speed on the MXS I2C IP.Signed-off-by: Marek Vasut
Cc: Stefano Babic
Cc: Fabio Estevam -
This patch pulls out the I2C speed setup from the i2c_init() call
and implements the bus configuration lookup table with register
values that needs to be programmed into the I2C IP to run at
particular speed.This patch is a first step towards implementing run-time I2C bus
speed configuration for the MXS I2C IP.Signed-off-by: Marek Vasut
Cc: Stefano Babic
Cc: Fabio Estevam -
Some functions in the MXC i2c driver were not static, fix this by
making them so.Signed-off-by: Marek Vasut
Cc: Heiko Schocher
Cc: Stefano Babic
