01 Dec, 2012
6 commits
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We don't want this for coreboot, so provide a way of compiling it out.
Signed-off-by: Gabe Black
Signed-off-by: Stefan Reinauer
Signed-off-by: Simon Glass -
We want to support VGA, serial, USB keyboard and the Coreboot memory
console buffer.Signed-off-by: Simon Glass
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This command is useful to allow to observe messages generated by
coreboot and u-boot until present. In particular it is handy when
u-boot is instrumented to fall through into console mode on startup
errors.Signed-off-by: Vadim Bendebury
Signed-off-by: Simon Glass -
This patch builds upon the recently introduced CBMEM console
feature of coreboot.CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:vvvvvvvvvvvvvvvvv
SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.Signed-off-by: Vadim Bendebury
Signed-off-by: Simon Glass -
Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.Signed-off-by: Stefan Reinauer
Signed-off-by: Vadim Bendebury
Signed-off-by: Gabe BlackSigned-off-by: Simon Glass
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sysinfo.c only contains the lib_sysinfo data structure which
is used/filled by tables.c. This split was introduced by importing
code from libpayload originally, but to keep the code simple, add
the single line of actual code to tables.cSigned-off-by: Stefan Reinauer
Signed-off-by: Simon Glass
29 Nov, 2012
16 commits
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We need an extra condition here in case we want to use fdt without the
silent console/cmdline editing/post options. It is easier to just remove
the #ifdef.Signed-off-by: Simon Glass
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Coreboot boards have an LPC TPM connected, so enable this.
Signed-off-by: Simon Glass
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Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.Signed-off-by: Simon Glass
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A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.This was tested as follows:
Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.Signed-off-by: Gabe Black
Signed-off-by: Vincent Palatin
Signed-off-by: Stefan Reinauer
Signed-off-by: Simon Glass -
This prevents the preprocessor from complaining when processing
variadic macrosSigned-off-by: Vadim Bendebury
Signed-off-by: Simon Glass
Acked-by: Graeme Russ -
U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.Signed-off-by: Gabe Black
Signed-off-by: Simon Glass
Acked-by: Graeme Russ -
coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another
commit)Signed-off-by: Stefan Reinauer
Signed-off-by: Simon Glass -
I suspect these includes were usually available because something else
included them earlier or because they were brought in transitively.Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988
Signed-off-by: Gabe Black
Signed-off-by: Simon Glass -
When running from coreboot we don't want this code.
This version works by ifdef-ing out all of the code that would go
into those sections and all the code that refers to it. The sections are
then empty, and the linker will either leave them empty for the loader
to ignore or remove them entirely.Signed-off-by: Gabe Black
Signed-off-by: Simon Glass -
These are available on other architectures, so add them on x86.
Signed-off-by: Simon Glass
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ilog2 is required by AHCI driver
Signed-off-by: Graeme Russ
Signed-off-by: Simon Glass -
Signed-off-by: Graeme Russ
Signed-off-by: Simon Glass -
Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stackSigned-off-by: Graeme Russ
Signed-off-by: Simon Glass -
So it can be used as a type in struct global_data and remove an ugly typecast
Signed-off-by: Graeme Russ
Signed-off-by: Simon Glass
Acked-by: Marek Vasut
28 Nov, 2012
18 commits
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Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibilityShould have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in
cpu_init.c.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.This requires adding a few bitfield macros for the BnTTLCRy0 register.
Signed-off-by: Timur Tabi
Signed-off-by: Andy Fleming -
Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.Signed-off-by: Yuanquan Chen
Signed-off-by: Andy Fleming -
board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :#ifdef CONFIG_FSL_SATA_V2
...
#endifTo solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bfSigned-off-by: Roy Zang
Signed-off-by: Andy Fleming -
The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied. For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.Signed-off-by: Timur Tabi
Signed-off-by: Andy Fleming -
by moving compat_strlist into the .bss section.
0xfe004d80 fdt_fixup_crypto_node [u-boot]: 264
Signed-off-by: Kim Phillips
Signed-off-by: Andy Fleming -
Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet
connector. It is necessary to use the same base address for correct LAW
address. An offset is added for NOR flash.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary). This is because the work-around is easier to implement
in PBI than in U-Boot itself.It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied. For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.Signed-off-by: Timur Tabi
Signed-off-by: Andy Fleming -
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.Signed-off-by: Timur Tabi
Signed-off-by: Shaohui Xie
Signed-off-by: Andy Fleming -
The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h. This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot. It's a holdover from the SDK.Signed-off-by: Timur Tabi
Signed-off-by: Andy Fleming -
Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning
of this virtual bank so that this bank can store RCW or be used together
with other banks to store large images.Signed-off-by: York Sun
Signed-off-by: Andy Fleming -
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming
Tested-by: Jaehoon Chung
Tested-by: Stephen Warren -
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.This patch does:
s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g
All 85xx, 86xx, and 83xx have been built with this change.
Signed-off-by: Andy Fleming
Tested-by: Andy Fleming
Acked-by: Kim Phillips -
If a malformed 'read' or 'write' command is issued, the Sandbox U-Boot
can crash because the command-handling code does no error checking on
the number of provided arguments.This change makes the mmc 'erase', 'read' and 'write' commands only
function if the proper number of arguments are supplied.Also puts the else assignment at the beginning fo the if() statement
to shortens the generated code. This removes an unnecessary jump from
the generated code.Signed-off-by: Taylor Hutt
Signed-off-by: Simon Glass
Signed-off-by: Andy Fleming
