06 Feb, 2020
1 commit
-
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
07 Jan, 2020
1 commit
-
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.Change to get system manager base address from DT node instead of
using #define.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
03 Dec, 2019
2 commits
-
These functions are CPU-related and do not use driver model. Move them to
cpu_func.hSigned-off-by: Simon Glass
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Tom Rini -
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.Move them over.
Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
24 Oct, 2019
3 commits
-
Remove macros which use PM_SIP_SVC offset and convert invoke_smc() to
xilinx_pm_request() which do calculation with PM_SIP_SVC already.Signed-off-by: Michal Simek
-
Use generic name instead of Versal specific because this should be also
used on ZynqMP.Signed-off-by: Michal Simek
-
versal_pm_request() and invoke_smc() are almost the same. Only one
difference is that versal_pm_request is adding PM_SIP_SVC offset to api_id.
The patch is moving platform implementation to firmware driver code for
synchronization.Signed-off-by: Michal Simek
Reviewed-by: Luca Ceresoli
08 Oct, 2019
4 commits
-
Use the new function from firmware version to get the firmware version.
Signed-off-by: Ibai Erkiaga
Signed-off-by: Michal Simek -
New firmware header to place firmware specific macro and function
declarations. The patch also moves the macros defining PM operations as
well as some helper macros.Signed-off-by: Ibai Erkiaga
Signed-off-by: Michal Simek -
No reason to define new_buf again.
Signed-off-by: Michal Simek
-
This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
30 Jul, 2019
8 commits
-
As already done for the 'pre' function, a check is added to not follow a
NULL pointer, if somebody has not assigned a 'post' function.Signed-off-by: Alexander Dahl
-
Some code parts stood too far left …
Signed-off-by: Alexander Dahl
-
Nothing special, but done before further cleanup.
* spacing
* braces
* __FUNCTION__ → __func__Suggested-by: Michal Simek
Signed-off-by: Alexander Dahl -
This adds support for slave serial programming, in addition to the
previously supported slave SelectMAP mode. There are two ways that this
can be used:-Using the clk and wdata callbacks in order to write image data one bit
at a time using pure bit-banging. This works, but is rather painfully
slow with typical image sizes.-By specifying the wbulkdata callback instead, the image loading process
can be offloaded to SPI hardware. In this mode the clk and wdata
callbacks do not need to be specified. This allows the image to be
loaded much faster, taking only a few seconds with even relatively large
images.Slave serial programming has been tested on the Kintex-7 series of
FPGAs.Signed-off-by: Robert Hancock
Signed-off-by: Michal Simek -
Some Xilinx FPGA configuration options can result in the startup
sequence extending past the end of the FPGA bitstream. Continue applying
CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure
the startup sequence is complete, as recommended by Xilinx.Signed-off-by: Robert Hancock
Signed-off-by: Michal Simek -
This is in preparation for adding slave serial programming support,
which uses the same pre/post operations as slave SelectMAP, to avoid
duplicating code.Signed-off-by: Robert Hancock
Signed-off-by: Michal Simek -
Add an option to allow this driver to be selected with Kconfig. As noted
in the description, this driver should also work with many newer Xilinx
FPGA families as the programming methods are essentially the same.Also added a missing FPGA_XILINX dependency to the similar Spartan 3
driver.Signed-off-by: Robert Hancock
Signed-off-by: Michal Simek -
Address Checkpatch warnings in virtex2 code prior to making other
changes. No functional change intended.Signed-off-by: Robert Hancock
Signed-off-by: Michal Simek
21 Jul, 2019
1 commit
-
Pin configuration of the FPGA devicetree block should be done
after core configuration in the arria10 fpga driver. This fix
corrects the check of status, and ensures that the fpga pin mux
is configured on correct configuration of the core fpga image.Signed-off-by: Dalon Westergreen
11 May, 2019
4 commits
-
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.Signed-off-by: Tien Fong Chee
-
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.Signed-off-by: Tien Fong Chee
-
Current watchdog reset is misplaced after for-loop status polling, so
this poses a risk that watchdog can't be reset timely if polling taking
longer than watchdog timeout. This patch moving the watchdog reset
into polling to ensure the watchdog can be reset timely.Signed-off-by: Tien Fong Chee
-
Ensure all the debug messages are always prefix with "FPGA: " and comment
beginning with uppercase letter.Signed-off-by: Tien Fong Chee
16 Apr, 2019
2 commits
-
Post configuration cant be run at u-boot as u-boot
didn't has any info about the design.So,this patch
adds an info message that post config was not run
and needs to be run manually if needed.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
Ensure the string for filename is always constant, otherwise it can be
corrupted by the writing.Signed-off-by: Tien Fong Chee
Signed-off-by: Michal Simek
18 Feb, 2019
1 commit
-
This patch prevent the Stratix 10 FPGA driver incorrectly return the
transaction ID as the mailbox error code. It should always return the
actual mailbox error code from SDM firmware.Signed-off-by: Ang, Chee Hong
24 Jan, 2019
1 commit
-
When FPGA programming fails, it does so silently, unless debugging
code is enabled. This makes it hard to detect problems in production
environments.Print the error message unconditionally so the error doesn't go
unnoticed.Signed-off-by: Luca Ceresoli
Signed-off-by: Michal Simek
21 Dec, 2018
2 commits
-
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.Signed-off-by: Ang, Chee Hong
-
Enable FPGA reconfiguration support for Stratix 10 SoC.
Signed-off-by: Ang, Chee Hong
31 Oct, 2018
1 commit
-
The 'status' variable in 'socfpga_load()' for both gen5 and arria10
is of type 'unsigned long' while it is always used as 'int' only.
Change it to 'int'.Signed-off-by: Simon Goldschmidt
26 Sep, 2018
1 commit
-
This patch modifies PL bitstream loading sequence as per
latest Xilfpga which supports all variants of bitstream images
generated from vivado and from bootgen. With this new change in
Xilfpga, uboot doesn't need to validate and swap bitstream as it will
be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting
PMUFW version before skipping the validation and swap sequence as there
can be old PMUFW which doesn't supports this feature. In this case, driver
uses old way of PL bitstream loading sequence.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
11 Sep, 2018
1 commit
-
Trivial Kconfig cleanup. Use tabs instead of spaces.
Signed-off-by: Michal Simek
19 Jul, 2018
2 commits
-
Disable the use of function zynq_loadfs when compiling
the driver for the SPL, as the following filesystem
functions are not found by the linker:
- fs_set_blk_dev
- fs_read
- fs_set_blk_dev
- fs_read
- fs_readSigned-off-by: Luis Araneda
Signed-off-by: Michal Simek -
This patch basically adds two new commands for loadig secure
images.
1. zynq rsa adds support to load secure image which can be both
authenticated or encrypted or both authenticated and encrypted
image in xilinx bootimage(BOOT.bin) format.
2. zynq aes command adds support to decrypt and load encrypted
image back to DDR as per destination address. The image has
to be encrypted using xilinx bootgen tool and to get only the
encrypted image from tool use -split option while invoking
bootgen.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
01 Jun, 2018
2 commits
-
This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen tool.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
This patch adds support to load secure bitstreams(authenticated or
encrypted or both). As of now, this feature is added and tested only
for xilinx bitstreams and the secure bitstream was generated using
xilinx bootgen tool, but the command is defined in more generic way.Command example to load authenticated and device key
encrypted bitstream is as follows
"fpga loads 0 100000 2000000 0 1"Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
07 May, 2018
1 commit
-
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
28 Apr, 2018
1 commit
-
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.Signed-off-by: Tom Rini
27 Apr, 2018
1 commit
-
Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")
Polling on wrong cleared bit. Fix with correct polling on bit is set.Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")
Signed-off-by: Tien Fong Chee