23 Jul, 2016
5 commits
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Signed-off-by: Ladislav Michl
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Add timeout to onenand_wait ready loop as it hangs here indefinitely
when chip not present. Once there, do the same for onenand_bbt_wait
as well (note: recent Linux driver code does the same)Signed-off-by: Ladislav Michl
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Use newly introduced function
Signed-off-by: Ladislav Michl
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Allow boards to runtime detect flash type.
Signed-off-by: Ladislav Michl
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Signed-off-by: Ladislav Michl
[trini: Adapt am33xx, duovero, omap_zoom1]
Signed-off-by: Tom RiniSigned-off-by: Tom Rini
22 Jul, 2016
35 commits
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identify_nand_chip hangs forever in loop when NAND is not present.
As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout
to let function fail gracefully allowing caller to know NAND is
not present. On NAND equipped board, reset succeeds on first read,
so 1000 loops seems to be safe timeout.Signed-off-by: Ladislav Michl
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Other payload than uImage is currently considered to be raw U-Boot
image. Check also for zImage in Falcon mode.Signed-off-by: Ladislav Michl
Reviewed-by: Heiko Schocher -
Add support for loading from UBI volumes on the top of NAND
and OneNAND.Signed-off-by: Ladislav Michl
Reviewed-by: Heiko Schocher -
Booting a payload out of NAND FLASH from the SPL is a crux today, as
it requires hard partioned FLASH. Not a brilliant idea with the
reliability of todays NAND FLASH chips.The upstream UBI + UBI fastmap implementation which is about to
brought to u-boot is too heavy weight for SPLs as it provides way more
functionality than needed for a SPL and does not even fit into the
restricted SPL areas which are loaded from the SoC boot ROM.So this provides a fast and lightweight implementation of UBI scanning
and UBI fastmap attach. The scan and logical to physical block mapping
code is developed from scratch, while the fastmap implementation is
lifted from the linux kernel source and stripped down to fit the SPL
needs.The text foot print on the board which I used for development is:
6854 0 0 6854 1abd
drivers/mtd/ubispl/built-in.oAttaching a NAND chip with 4096 physical eraseblocks (4 blocks are
reserved for the SPL) takes:In full scan mode: 1172ms
In fastmap mode: 95msThe code requires quite some storage. The largest and unknown part of
it is the number of fastmap blocks to read. Therefor the data
structure is not put into the BSS. The code requires a pointer to free
memory handed in which is initialized by the UBI attach code itself.See doc/README.ubispl for further information on how to use it.
This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi
There is no way to share the fastmap code, as UBISPL only utilizes the
slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap()
from the original kernel ubi fastmap implementation.Signed-off-by: Thomas Gleixner
Signed-off-by: Ladislav Michl
Acked-by: Heiko Schocher
Reviewed-by: Tom Rini -
Signed-off-by: Ladislav Michl
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To support UBI in SPL we need a simple NAND read function. Add one to
nand_spl_simple and keep it as simple as it goes.Signed-off-by: Thomas Gleixner
Signed-off-by: Ladislav Michl
Acked-by: Scott Wood
Reviewed-by: Tom Rini
Reviewed-by: Heiko Schocher -
Signed-off-by: Ladislav Michl
Reviewed-by: Tom Rini
Reviewed-by: Heiko Schocher -
This patch implements the reading functionality for the generic I2C
EEPROM driver, which was just a non-functional stub until now.Since the page size will be of importance for the writing support, we
add suitable members to the private data structure to keep track of it.Compatibility strings for a range of at24c* chips are added.
Signed-off-by: Mario Six
Reviewed-by: Simon Glass
Reviewed-by: Heiko Schocher -
Remove unnecessary board specifc config files for
zynq boards(microzed, picozed, ZC770(all), zed) and point
to zynq common config file.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
Enable config CONFIG_SYS_NO_FLASH through defconfig
for all zynq boards.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
Move config option CONFIG_SYS_NO_FLASH as Kconfig
option. All the boards which needs to enable this
option can be done through defconfigsSigned-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
Define config USB_STORAGE through defconfig for all
respective zynq boardsSigned-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
Add Kconfig entry config option for USB_EHCI_ZYNQ
and update the same to enable for all zynq boards
which supports USBSigned-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
The EP platform also has working AHCI emulation, so I see little reason
not to implement the plumbing for it that enables us to boot from AHCI.Signed-off-by: Alexander Graf
Signed-off-by: Michal Simek -
Code around was removed because of move to Kconfig.
Signed-off-by: Michal Simek
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Simple version of clk_get_by_index() added by:
"dm: clk: Add a simple version of clk_get_by_index()"
(sha1: a4b10c088c4f6ef2e2bba33e8cfea369bcbbce44)
is only working for #clock-cells= but not for
any other values. Fixed clocks is using #clock-cells=
which requires full implementation.Remove simplified versions of clk_get_by_index() and use full version.
Also remove empty clk_get_by_name() which is failing when it is called
which is useless.Signed-off-by: Michal Simek
Acked-by: Stephen Warren -
ZynqMP will use reading clock freq directly from DT.
Signed-off-by: Michal Simek
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Read information about clock frequency from DT.
Signed-off-by: Michal Simek
Reviewed-by: Simon Glass
Reviewed-by: Moritz Fischer -
Compile SPL for all boards even psu_init.c/h files are not in the tree
yet. But this change enables covering SPL issues in mainline.Signed-off-by: Michal Simek
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Serial driver starts to use clk framework that's why
enable it by default.Signed-off-by: Michal Simek
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Make code 64bit aware.
Warnings:
+../arch/arm/lib/spl.c: In function ‘jump_to_image_linux’:
+../arch/arm/lib/spl.c:63:3: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
+../common/spl/spl_fat.c: In function ‘spl_load_image_fat’:
+../common/spl/spl_fat.c:91:33: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]Signed-off-by: Michal Simek
Reviewed-by: Simon Glass -
Disable internal clock by clearing the internal
clock enable bit. This bit needs to be cleared too
when we stop the SDCLK for changing the frequency
divisor. This bit should be set to zero when the
device is not using the Host controller.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
When CONFIG_API is selected with DM_ETH this
error is present:
api/api_net.c: In function 'dev_enum_net':
api/api_net.c:61:35: warning: initialization from incompatible pointer
type
struct eth_device *eth_current = eth_get_dev();
^
api/api_net.c:68:39: error: dereferencing pointer to incomplete type
memcpy(di->di_net.hwaddr, eth_current->enetaddr, 6);
^
Disable api_net functions when ETH_DM is selected.Signed-off-by: Chris Johns
Signed-off-by: Michal Simek -
Based on:
"ARM: uniphier: use the default CONFIG_BOOTDELAY=2"
(sha1: 7c8ef0feb97586d35b0296b48903daef8c06ab21)"I do not insist on CONFIG_BOOTDELAY=3. The default value in Kconfig,
CONFIG_BOOTDELAY=2, is just fine for these boards."Reported-by: Masahiro Yamada
Signed-off-by: Michal Simek -
Per Vikas' request, the problem this commit is supposed to be solving is
something he doesn't see and further this introduces additional hardware
requirements.This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440.
Signed-off-by: Tom Rini
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Loading the fdt at 0xc00000 fails if the uncompressed kernel image is
greater than 12 MiB, which is quite common with modern kernels and
multiplatform defconfigs. Move fdtaddr to 0x1e00000 which is just under
the ramdiskaddr on most targets.Signed-off-by: Scott Wood
Cc: Peter Tyser
Cc: Dirk Eibach
Cc: Andy Fleming
Cc: Paul Gortmaker
Acked-by: Paul Gortmaker
Reviewed-by: York Sun -
Adds information regarding SPL handling validation process of main u-boot
image on power/mpc85xx and arm/layerscape platforms.Signed-off-by: Sumit Garg
Reviewed-by: Simon Glass
Reviewed-by: York Sun -
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.The changes are similar to
commit 467a40dfe35f48d830f01a72617207d03ca85b4d
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.Reviewed-by: Ruchika Gupta
Reviewed-by: Simon Glass
Signed-off-by: Aneesh Bansal
Signed-off-by: Sumit Garg
Reviewed-by: York Sun -
As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.Reviewed-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
Signed-off-by: Sumit Garg
Reviewed-by: Simon Glass
Reviewed-by: York Sun -
Due to the blow up of the latest kernel size, the default gnuzip
size (8M) seems too small. The yocto kernel size I built for
mpc8315erdb board is 5294393, and it can't be boot by using the
latest u-boot. So expand gnuzip buffer for all the mpc83xx boards
to fix this issue.Robert P. J. Day also pointed that the kernel partition on the NAND
flash is also too small, fix it at the same time.Reported-by: Robert P. J. Day
Signed-off-by: Kevin Hao
Reviewed-by: York Sun -
Robert P. J. Day has pointed that the value of SYS_MONITOR_LEN in
MPC8315ERDB.h is smaller than the u-boot.bin. This will cause the
overlap between the code of u-boot and the environment variable.
So when executing saveenv, it will corrupt the code of u-boot and
causes the board not boot. Fix this for all the mpc83xx boards by
reserving a 512K area.Reported-by: Robert P. J. Day
Signed-off-by: Kevin Hao
Reviewed-by: York Sun -
On Tegra186, U-Boot is booted by the binary firmware as if it were a
Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address
of that DTB, and parse the /memory/reg property to determine the actual
RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use.Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion
that U-Boot use that DTB as its control DTB. I don't believe that would
work well, so I do not plan to put any effort into this. By default the
FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT
bindings. U-Boot aims to use only upstreamed DT bindings, or as close as
it can get. Replacing this DTB with a DTB using upstream bindings is
physically quite easy; simply replace the content of one of the GPT
partitions on the eMMC. However, the binary FW at least partially relies
on the existence/content of some nodes in the DTB, and that requires the
DTB to be written according to downstream bindings. Equally, if U-Boot
continues to use appended DTBs built from its own source tree, as it does
for all other Tegra platforms, development and deployment is much easier.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren
