14 Oct, 2008
12 commits
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The checks for CFG_EEPROM_PAGE_WRITE_ENABLE and
CFG_EEPROM_PAGE_WRITE_BITS in various temperature
sensor drivers are not necessarySigned-off-by: Peter Tyser
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Since we're working with unsigned data, you can't apply a signed pointer
cast and then attempt to print the result. Otherwise you get wrong output
when the sign bit is set like "0xFF" incorrectly extended to "0xFFFFFFFF".Signed-off-by: Mike Frysinger
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We don't need CONFIG_CFG_STRINGS anymore now that we have the define
CONFIG_CMD_STRINGS and Makefile control.Signed-off-by: Mike Frysinger
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When the total size of all NAND devices exceeds 4 GiB, the size will
overflow. This patch tries to fix this.Note that we still have a problem when a single NAND device is bigger
than 4 GiB: then the overflow would actually happen earlier, i. e.
when storing the size in nand_info[].size, as nand_info[].size is an
"u_int32_t".Signed-off-by: Jason Jin
Signed-off-by: Wolfgang Denk -
Signed-off-by: Louis Su
Signed-off-by: Ben Warren -
Currently VSC8601 doesn't link with 10/100M partners if the
EEPROM/Strapping is not set up.
Setting the auto-neg register fixes this.Signed-off-by: Andre Schwarz
Signed-off-by: Ben Warren -
get_prom function was used __attriute__ , but it is not enable.
ax88796.o does not do link besides ne2000.o. When ld is carried
out, get_prom function of ax88796.c is ignored.
This problem is a thing by specifications of ld.
I checked and test this patch on SuperH and MIPS.Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Ben Warren -
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu -
Address calculated in EXPORT_FUNC in SuperH was wrong, I revised it.
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Ed Swarthout
Acked-by: Andy Fleming
13 Oct, 2008
13 commits
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This is no longer necessary now that the GD_FLG_RELOC flag is set for
all ARM boards.Signed-off-by: Hugo Villeneuve
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Signed-off-by: Luigi 'Comio' Mantellini
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This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.Signed-off-by: Nick Spence
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For some reason we duplicated the majority of code in lib_ppc/interrupts.c
Not know how that happened, but there is no good reason for it.Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.Signed-off-by: Kumar Gala
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The flash_unlock_seq requires a sector for AMD_LEGACY.
Fix a retcode check typeo.Signed-off-by: Ed Swarthout
Signed-off-by: Stefan Roese
10 Oct, 2008
4 commits
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This patch fixes USB 2.0 communication issues on some DU440 boards.
Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese -
Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese -
Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese -
Signed-off-by: Matthias Fuchs
Signed-off-by: Stefan Roese
09 Oct, 2008
7 commits
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Commit 445a7b38308eb05b41de74165b20855db58c7ee5 introduced the following
compile warnings:cmd_i2c.c:112: warning: missing braces around initializer
cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]')Signed-off-by: Kumar Gala
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Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the
MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
correct. There seems to be an error in the 8544 RM.Signed-off-by: Wolfgang Grandegger
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get_cpu_board_revision() returned board revision based on information stored
in global static struct eeprom. It should instead use one from local struct
board_eeprom, to which the data is actually read from EEPROM. The bug led to
system hang after printing L1 cache information on U-Boot startup. The problem
was observed on MPC8555CDS system and possibly affects other Freescale MPC85xx
boards using CFG_I2C_EEPROM_CCID.The change has been successfully tested on MPC8555CDS system.
Signed-off-by: Rafal Czubak
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
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Switch to the standard CFG_HZ=1000 value, while at it, minor white-space
cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads,
provides 2% or 0.4% precision depending on the
CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s
boot-delay.Signed-off-by: Guennadi Liakhovetski
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due to the arm implementation which supposed that U-Boot is in RAM
when we jump to start_armbootSigned-off-by: gnusercn
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
08 Oct, 2008
4 commits
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After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.Signed-off-by: Adam Graham
Signed-off-by: Victor Gallardo
Signed-off-by: Stefan Roese -
Signed-off-by: Haiying Wang
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The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for
system information like mac addresses etc. This patch enables it.Signed-off-by: Haiying Wang
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MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.Signed-off-by: Haiying Wang
