31 Jan, 2018
1 commit
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DDR4 RDIMM has some information in SPD to be used to calculate the
control words for register chip. The rest can be found from JEDEC
spec DDR4RCD02.Signed-off-by: York Sun
19 Jan, 2016
1 commit
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In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.Signed-off-by: Tom Rini
23 Apr, 2014
1 commit
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Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.Signed-off-by: York Sun
17 Oct, 2013
1 commit
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Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.plConvert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.Signed-off-by: Priyanka Jain
15 Oct, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini
24 Aug, 2012
1 commit
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When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.Signed-off-by: York Sun
Signed-off-by: Andy Fleming
29 Nov, 2011
1 commit
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Newer JEDEC DDR3 SPD Specifications define several additional values for
the DDR3 module_type field which were undefined when this code was
written. Update the code to handle the newer module types.Signed-off-by: Ira W. Snyder
Cc: York Sun
Signed-off-by: Kumar Gala
12 Jul, 2011
1 commit
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Adding byte 32 and 33
Signed-off-by: York Sun
Signed-off-by: Kumar Gala
04 Apr, 2011
1 commit
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The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.Signed-off-by: Kyle Moffett
Cc: Andy Fleming
Cc: Kim Phillips
Acked-by: York Sun
Signed-off-by: Kumar Gala
27 Jul, 2010
1 commit
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Enabled registered DIMMs using data from SPD. RDIMMs have registers
which need to be configured before using. The register configuration
words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
should read those RCWs and put into DDR controller before initialization.Signed-off-by: York Sun
31 Mar, 2009
1 commit
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- support mirrored DIMMs, not support register DIMMs
- test passed on P2020DS board with MT9JSF12872AY-1G1D1
- test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1Signed-off-by: Dave Liu
Signed-off-by: Travis Wheatley
27 Aug, 2008
1 commit
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Also adds helper functions for DDR1/2 to verify the checksum.
Signed-off-by: Kumar Gala