Eric Lee / smarc-uboot

03 Jun, 2017

1 commit

  • 6de046eaa   net: macb: Fix GMAC not work when enable DM_ETH ... Browse Code »

    Always search the PHY to determine the macb->phy_addr before using
    the PHY to fix "No PHY present" error.

    Fix the wrong test of the GMAC's phy interface mode, it should be
    PHY_INTERFACE_MODE_RGMII.

    Signed-off-by: Wenyou Yang
    Reviewed-by: Simon Glass
    Acked-by: Joe Hershberger

    Wenyou Yang
     

01 Jun, 2017

1 commit

  • a821c4af7   dm: Rename dev_addr..() functions ... Browse Code »

    These support the flat device tree. We want to use the dev_read_..()
    prefix for functions that support both flat tree and live tree. So rename
    the existing functions to avoid confusion.

    In the end we will have:

    1. dev_read_addr...() - works on devices, supports flat/live tree
    2. devfdt_get_addr...() - current functions, flat tree only
    3. of_get_address() etc. - new functions, live tree only

    All drivers will be written to use 1. That function will in turn call
    either 2 or 3 depending on whether the flat or live tree is in use.

    Note this involves changing some dead code - the imx_lpi2c.c file.

    Signed-off-by: Simon Glass

    Simon Glass
     

10 May, 2017

2 commits

02 Mar, 2017

1 commit

10 Feb, 2017

1 commit

08 Feb, 2017

3 commits

02 Oct, 2016

1 commit

24 Sep, 2016

1 commit

16 Aug, 2016

2 commits

13 Jun, 2016

3 commits

  • f1dcc19b2   net: macb: Convert to driver model ... Browse Code »
    17

    Add driver-model support to this driver. The old code remains for now so
    that we can convert boards one at a time.

    Signed-off-by: Simon Glass
    Reviewed-by: Heiko Schocher
    Tested-on: smartweb, corvus, taurus, axm
    Tested-by: Heiko Schocher
    Acked-by: Joe Hershberger
    Reviewed-by: Andreas Bießmann

    Simon Glass
     
  • f589f8cca   net: macb: Flush correct cache portion when sending ... Browse Code »

    The end address of the cache flush must be cache-line-aligned since
    otherwise (at least on ARM926-EJS) the request is ignored. When the cache
    is enabled this means that packets are not sent.

    Signed-off-by: Simon Glass
    Reviewed-by: Heiko Schocher
    Acked-by: Joe Hershberger
    Reviewed-by: Andreas Bießmann

    Simon Glass
     
  • d5555b70e   net: macb: Prepare for driver-model conversion ... Browse Code »

    Adjust this driver to avoid using struct netdev in functions that driver
    model will call. Also refactor the receive function to be compatible with
    driver model.

    Signed-off-by: Simon Glass
    Reviewed-by: Heiko Schocher
    Tested-on: smartweb, corvus, taurus, axm
    Tested-by: Heiko Schocher
    Reviewed-by: Joe Hershberger
    Acked-by: Joe Hershberger
    Reviewed-by: Andreas Bießmann

    Simon Glass
     

06 May, 2016

1 commit

27 Jan, 2016

1 commit

  • 75b03cf14   net: macb: Not all the GEM are gigabit capable ... Browse Code »

    During the initialization of PHY the gigabit bit capable is set if the
    controller is a GEM. However, for sama5d2 and sama5d4, the GEM is
    configured to support only 10/100.

    Improperly setting the GBE capability leads to an unresponsive MAC
    controller. This patch fixes this behavior allowing using the gmac with
    these SoCs.

    Suggested-by: Nicolas Ferre
    Signed-off-by: Gregory CLEMENT
    Acked-by: Nicolas Ferre
    Acked-by: Joe Hershberger
    Reviewed-by: Andreas Bießmann
    [fixed minor checkpatch warning]
    Signed-off-by: Andreas Bießmann

    Gregory CLEMENT
     

12 Aug, 2015

1 commit

  • ade4ea4d7   net: macb: add gmac multi-queue support ... Browse Code »

    This patch refer to linux kernel commit: d8b763e1e79f
    net/macb: add TX multiqueue support for gem
    by: Cyrille Pitchen

    1. macb driver will check the register to find how many queues support for
    this chip.

    2. Then as we only use queue0 for tx, so we will set up all other queues
    use a dummy descriptor, which USED bit is set. So those queues are not used.

    Signed-off-by: Josh Wu
    Acked-by: Joe Hershberger

    Wu, Josh
     

20 May, 2015

1 commit

  • f566c9949   net: Update hardware MAC address if it changes in env ... Browse Code »
    41

    When the ethaddr changes in the env, the hardware should also be updated
    so that MAC filtering will work properly without resetting U-Boot.

    Also remove the manual calls to set the hwaddr that was included in a
    few drivers as a result of the framework not doing it.

    Reported-by: Michal Simek
    Signed-off-by: Joe Hershberger
    Tested-by: Michal Simek

    Joe Hershberger
     

19 Apr, 2015

2 commits

19 Mar, 2015

1 commit

17 Nov, 2014

2 commits

  • cabf61ce4   net: macb: enable GMAC IP without GE feature support ... Browse Code »

    The User Register in GMAC IP is used to select interface type.
    When with GE feature, it is used to select interface between
    RGMII and GMII. If without GE feature, it is used to select
    interface between MII and RMII.

    Signed-off-by: Bo Shen
    Signed-off-by: Andreas Bießmann

    Bo Shen
     
  • b2eff0886   net: macb: write mac address when initialization ... Browse Code »

    When boot up without mac address setting, it will give the warning
    message like: "Warning: failed to set MAC address", however when
    execute network related command, it still execute them without any
    warning information.

    With this patch, it will exit directly with following information:
    "gmac0: mac address is not valid"

    It also solve the problem after bootup then set mac address and the
    mac address won't set to net device issue.

    Signed-off-by: Bo Shen
    Tested-by: Boris Brezillon
    Signed-off-by: Andreas Bießmann

    Bo Shen
     

11 Oct, 2014

1 commit

15 Jun, 2014

2 commits

  • 5ae0e3827   net: macb: enable dcache in macb ... Browse Code »

    Add to code to flush the dcache after we writing in DMA buffer.
    Also we need invalidate the dcache before we check the status in the
    DMA buffer.

    Tested in SAMA5D3x-EK with gmac0. Tftp download speed shows in below:
    Disable DCache: 1.1 MiB/s
    Enable DCache: 1.6 MiB/s
    Increase speed with about 40%.

    The code should have no impact with the boards which are not
    enable_dcache().
    Tested in AT91SAM9M10G45EK.

    Signed-off-by: Josh Wu
    Signed-off-by: Andreas Bießmann

    Wu, Josh
     
  • ceef983bf   macb: make checkpatch clean ... Browse Code »

    This also renames the CONFIG_SYS_MACB_xx defines. They are used just local and
    therefore don't need the CONFIG_SYS_ prefix.

    Signed-off-by: Andreas Bießmann
    Reviewed-by: Josh Wu

    Andreas Bießmann
     

05 Nov, 2013

1 commit

22 Aug, 2013

1 commit

24 Jul, 2013

1 commit

25 Jun, 2013

5 commits

05 Nov, 2012

1 commit

  • eef1cf2d5   include/linux/byteorder: import latest endian definitions from linux ... Browse Code »

    u-boot's byteorder headers did not contain endianness attributions
    for use with sparse, causing a lot of false positives. Import the
    kernel's latest definitions, and enable them by including compiler.h
    and types.h. They come with 'const' added for some swab functions, so
    fix those up, too:

    include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

    Also, note: u-boot's historic __BYTE_ORDER definition has been
    preserved (for the time being at least).

    We also remove ad-hoc barrier() definitions, since we're including
    compiler.h in files that hadn't in the past:

    macb.c:54:0: warning: "barrier" redefined [enabled by default]

    In addition, including compiler.h in byteorder changes the 'noinline'
    definition to expand to __attribute__((noinline)). This fixes
    arch/powerpc/lib/bootm.c:

    bootm.c:329:16: error: attribute '__attribute__': unknown attribute
    bootm.c:329:16: error: expected ')' before '__attribute__'
    bootm.c:329:25: error: expected identifier or '(' before ')' token

    powerpc sparse builds yield:

    include/common.h:356:22: error: marked inline, but without a definition

    the unknown-reason inlining without a definition is considered obsolete
    given it was part of the 2002 initial commit, and no arm version was
    'fixed.'

    also fixed:
    ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

    and:

    Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
    make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
    make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
    powerpc-fsl-linux-size: './u-boot': No such file
    4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
    include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
    4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

    and:

    In file included from crc32.c:50:0:
    crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
    crc32table.h:4:1: error: initializer element is not constant
    crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

    Signed-off-by: Kim Phillips
    [trini: Remove '#endif' in include/common.h around setenv portion]
    Signed-off-by: Tom Rini

    Kim Phillips
     

04 Sep, 2012

2 commits

01 Sep, 2012

1 commit

  • f7fa2f374   arm : Atmel : add at91sam9x5ek board support ... Browse Code »

    Add at91sam9x5ek board support, this board support the following SoCs
    AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35

    Using at91sam9x5ek_nandflash to configure for the board
    Now only supports NAND with software ECC boot up

    Signed-off-by: Bo Shen
    [move MAINTAINERS entry to right place]
    Signed-off-by: Andreas Bießmann

    Bo Shen