Eric Lee / smarc-uboot

24 Oct, 2019

1 commit

15 Oct, 2019

1 commit

11 Oct, 2019

1 commit

30 Sep, 2019

1 commit

29 Sep, 2019

1 commit

  • 77ac4a3e3   MLK-22444-2: nand: mxs_nand: add API for switching different BCH layouts ... Browse Code »

    On i.MX7 in a sake of reducing the disturbances caused by a neighboring
    cells in the FCB page in the NAND chip, a randomizer is enabled when
    reading the FCB page by ROM bootloader.

    Add API for setting BCH to specific layout (and restoring it back) used by
    ROM bootloader to be able to burn it in a proper way to NAND using
    nandbcb command.

    Signed-off-by: Igor Opaniuk
    Signed-off-by: Anti Sullin

    Signed-off-by: Alice Guo
    (cherry picked from commit eaba02830252ed044e319571a7f3ebed412ae93b)

    Igor Opaniuk
     

16 Jul, 2019

1 commit

  • 49538a259   i.MX6: nand: add nandbcb command for imx ... Browse Code »

    Writing/updating boot image in nand device is not
    straight forward in i.MX6 platform and it requires
    boot control block(BCB) to be configured.

    It becomes difficult to use uboot 'nand' command to
    write BCB since it requires platform specific attributes
    need to be taken care of.

    It is even difficult to use existing msx-nand.c driver by
    incorporating BCB attributes like mxs_dma_desc does
    because it requires change in mtd and nand command.

    So, cmd_nandbcb implemented in arch/arm/mach-imx

    BCB contains two data structures, Firmware Configuration Block(FCB)
    and Discovered Bad Block Table(DBBT). FCB has nand timings,
    DBBT search area, page address of firmware.

    On summary, nandbcb update will
    - erase the entire partition
    - create BCB by creating 2 FCB/DBBT block followed by
    1 FW block based on partition size and erasesize.
    - fill FCB/DBBT structures
    - write FW/SPL on FW1
    - write FCB/DBBT in first 2 blocks

    for nand boot, up on reset bootrom look for FCB structure in
    first block's if FCB found the nand timings are loaded for
    further reads. once FCB read done, DTTB will load and finally
    firmware will be loaded which is boot image.

    Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
    information.

    Signed-off-by: Jagan Teki
    Signed-off-by: Sergey Kubushyn
    Signed-off-by: Shyam Saini
    Signed-off-by: Han Xu

    Shyam Saini
     

13 Jun, 2019

1 commit

24 May, 2019

10 commits

  • 99b54a696   MLK-12483-4 mx6: Modify drivers to disable fused modules ... Browse Code »
    12

    Add the fuse checking in drivers, when the module is disabled in fuse,
    the driver will not work.

    Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
    USB-EHCI, GIS, LCDIF and EPDC.

    Signed-off-by: Ye Li
    (cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
    (cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
    (cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db)

    Ye Li
     
  • e39d35e95   MLK-21851 mxs_nand: Update compatible string for i.MX6SX ... Browse Code »
    11

    The iMX6SX uses compatible string "fsl,imx6sx-gpmi-nand" for gpmi
    node in DTS, so update the driver for the string

    Signed-off-by: Ye Li

    Ye Li
     
  • 72cf8b976   MLK-21844-2 MXS_NAND: Add clock support for iMX8 ... Browse Code »
    11

    Since iMX8 has enabled clock uclass, we can parse the clocks from DTB
    and enable them in GPMI driver.

    Signed-off-by: Ye Li

    Ye Li
     
  • a9f0815c2   MLK-16034-02: enable GPMI NAND driver for i.MX8 ... Browse Code »
    11

    enable the GPMI NAND driver for i.MX8, the major changes

    - register defination for i.mx8
    - Makefile change for misc.c
    - DMA structure must be 32bit address

    Signed-off-by: Han Xu
    (cherry picked from commit 474c4270108551647c7064a23abdc2e11d7f37ab)
    (cherry picked from commit 029cce25cce94c30dd0305bb9b17ba7f939ee1af)

    Han Xu
     
  • 45e34020f   MLK-17153-1 nand: Update SPL MXS NAND mini driver ... Browse Code »
    11

    Update the mini driver to add support for getting ecc info from ONFI and
    support read image data from page unaligned NAND address.

    Signed-off-by: Ye Li

    Ye Li
     
  • cac7f6b24   MLK-17109-3 mxs_nand: Add support for i.MX8M ... Browse Code »
    11

    Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M.

    Signed-off-by: Ye Li
    (cherry picked from commit 6cb839cabb42b81e37214e00448fc5dac89fd1f1)
    (cherry picked from commit 468509f86a2d040398aa6b019bb6644bfb0ef11c)

    Ye Li
     
  • 722f0ff0b   MLK-12693-2 nand: mxs: correct bitflip for erased NAND page ... Browse Code »
    11

    This patch is a porting of
    http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
    "
    i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
    bitflip number for erased NAND page. So for these two platform, set the
    erase threshold to gf/2 and if bitflip detected, GPMI driver will
    correct the data to all 0xFF.

    Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
    with the one for i.MX6QP.
    "

    In this patch, i.MX6UL is added and threshold changed to use ecc_strength.

    Signed-off-by: Peng Fan
    (cherry picked from commit 489929be0221bb7d4c46bb5bc6083650b78f73e0)
    Signed-off-by: Ye Li
    (cherry picked from commit 37d7f9614aa357f270312d7ceaab0f7006dc5aea)
    (cherry picked from commit 5f50a850dd42d28b6105ee7e1b4b1822e7ba569b)

    Peng Fan
     
  • eefb30b8e   MLK-12693-1 nand: mxs: fix the bitflips for erased page when uncorrectable error ... Browse Code »
    11

    This patch is porting from linux:
    http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768

    "
    We may meet the bitflips in reading an erased page(contains all 0xFF),
    this may causes the UBIFS corrupt, please see the log from Elie:

    -----------------------------------------------------------------
    [ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
    ...
    [ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
    [ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
    [ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
    -----------------------------------------------------------------

    This patch does a check for the uncorrectable failure in the following steps:

    [0] set the threshold.
    The threshold is set based on the truth:
    "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
    do the ECC."

    For the sake of safe, we will set the threshold with half the gf_len, and
    do not make it bigger the ECC strength.

    [1] count the bitflips of the current ECC chunk, assume it is N.

    [2] if the (N
    (cherry picked from commit ceb324a2914487aa517a6c70a06a20b5e3438fda)
    (cherry picked from commit 026751697e41c7376414a8716cf0ea4bf998b85f)
    (cherry picked from commit 93b481f07b8cb59c733f420bebea77ac484f9036)

    Peng Fan
     
  • 71253252c   MLK-12601: mtd: gpmi: provide the option to use legacy bch geometry ... Browse Code »
    11

    Provide an option in DT to use legacy bch geometry, which compatible
    with the 3.10 kernel bch setting. To enable the feature, adding
    "fsl,legacy-bch-geometry" under gpmi-nand node.

    NOTICE: The feature must be enabled/disabled in both u-boot and kernel.

    Signed-off-by: Han Xu
    Signed-off-by: Ye Li

    Ye Li
     
  • 71fe512f8   MLK-11719-4: mtd: gpmi: change the BCH layout setting for large oob NAND ... Browse Code »
    11

    The code change updated the NAND driver BCH ECC layout algorithm to
    support large oob size NAND chips(oob > 1024 bytes) and proposed a new
    way to set ECC layout.

    Current implementation requires each chunk size larger than oob size so
    the bad block marker (BBM) can be guaranteed located in data chunk. The
    ECC layout always using the unbalanced layout(Ecc for both meta and
    Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
    cannot support because BCH doesn’t support GF 15 for 2K chunk.

    The change keeps the data chunk no larger than 1k and adjust the ECC
    strength or ECC layout to locate the BBM in data chunk. General idea for
    large oob NAND chips is

    1.Try all ECC strength from the minimum value required by NAND spec to
    the maximum one that works, any ECC makes the BBM locate in data chunk
    can be chosen.

    2.If none of them works, using separate ECC for meta, which will add one
    extra ecc with the same ECC strength as other data chunks. This extra
    ECC can guarantee BBM located in data chunk, of course, we need to check
    if oob can afford it.

    Previous code has two methods for ECC layout setting, the
    legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference
    between these two methods is, legacy_calc_ecc_layout set the chunk size
    larger chan oob size and then set the maximum ECC strength that oob can
    afford. While the calc_ecc_layout_by_info set chunk size and ECC
    strength according to NAND spec. It has been proved that the first
    method cannot provide safe ECC strength for some modern NAND chips, so
    in current code,

    1. Driver read NAND parameters first and then chose the proper ECC
    layout setting method.

    2. If the oob is large or NAND required data chunk larger than oob size,
    chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info

    3. legacy_calc_ecc_layout only used for some NAND chips does not contains
    necessary information. So this is only a backup plan, it is NOT
    recommended to use these NAND chips.

    Signed-off-by: Han Xu
    Signed-off-by: Ye Li

    Ye Li
     

13 Mar, 2019

1 commit

  • d46d27d3b   MTD: mxs_nand_spl: Redo the way nand_init initializes ... Browse Code »

    Currently the spl system calls nand_init which does nothing.
    It isn't until an attempt to load from NAND that it gets initialized.
    Subsequent attempts to load just skip the initialization because
    NAND is already initialized.

    This moves the contents of mxs_nand_init to nand_init. In the event
    of an error, it clears the number of nand chips found. Any
    attempts to use nand will check if there are nand chips available
    instead of actually doing the initialization at that time. If there
    are none, it will return an error to the higher level calls.

    Signed-off-by: Adam Ford

    Adam Ford
     

15 Feb, 2019

3 commits

29 Jan, 2019

1 commit

24 Jan, 2019

1 commit

21 Jan, 2019

1 commit

  • 49ad40298   ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig ... Browse Code »
    25

    This commit converts the following items to Kconfig:

    CONFIG_ATMEL_NAND_HWECC
    CONFIG_ATMEL_NAND_HW_PMECC
    CONFIG_PMECC_CAP
    CONFIG_PMECC_SECTOR_SIZE
    CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

    [PMECC References]
    https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
    https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap

    [Mailing List Thread]
    https://lists.denx.de/pipermail/u-boot/2018-December/350666.html

    Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
    [trini: Make the migration be size neutral and possibly not fix the
    above in all cases]
    Reported-by: Daniel Evans
    Cc: Eugen Hristev
    Signed-off-by: Derald D. Woods
    Signed-off-by: Tom Rini

    Derald D. Woods
     

17 Jan, 2019

1 commit

03 Jan, 2019

1 commit

02 Jan, 2019

1 commit

01 Jan, 2019

4 commits

29 Dec, 2018

3 commits

  • 9d43649a7   mtd: rawnand: denali: fix a race condition when DMA is kicked ... Browse Code »

    Based on Linux commit cf51e4b9c34407bf0c3d9b582b7837e047e1df47

    Add the register read-back, commenting why this is necessary.

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     
  • 8ccfbfb3e   mtd: rawnand: denali: optimize timing parameters for data interface ... Browse Code »

    Based on Linux commit 1dfac31a5a63ac04a9b5fbc3f5105a586560f191

    This commit improves the ->setup_data_interface() hook.

    The denali_setup_data_interface() needs the frequency of clk_x
    and the ratio of clk_x / clk.

    The latter is currently hardcoded in the driver, like this:

    #define DENALI_CLK_X_MULT 6

    The IP datasheet requires that clk_x / clk be 4, 5, or 6. I just
    chose 6 because it is the most defensive value, but it is not optimal.
    By getting the clock rate of both "clk" and "clk_x", the driver can
    compute the timing values more precisely.

    To not break the existing platforms, the fallback value, 50 MHz is
    provided. It is true for all upstreamed platforms.

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     
  • a13fe7afe   mtd: rawnand: denali_dt: add more clocks based on IP datasheet ... Browse Code »

    Based on Linux commit 6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5

    Currently, denali_dt.c requires a single anonymous clock, but
    the Denali User's Guide requires three clocks for this IP:

    - clk: controller core clock

    - clk_x: bus interface clock

    - ecc_clk: clock at which ECC circuitry is run

    This commit supports these named clocks to represent the real hardware.

    For the backward compatibility, the driver still accepts a single clock
    just as before. The clk_x_rate is taken from the clock driver again if
    the named clock "clk_x" is available. This will happen only for future
    DT, hence the existing DT files are not affected.

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     

06 Dec, 2018

1 commit

26 Nov, 2018

1 commit

  • 1cefca71d   mtd: nand: Arasan: Add subpage configuration support ... Browse Code »

    Add support for disabling subpage write support via
    CONFIG_SYS_NAND_NO_SUBPAGE_WRITE.

    Currently the Linux Arasan driver does not support subpage writes and in
    case of running UBI and accessing the same UBI volume from both U-Boot
    and Linux it is required to have the same subpage write configuration
    else the location of the UBI headers (EC + VID) will be misaligned
    (subpage vs page) and incompatible. Hence the need for disabling
    subpage write support in the U-Boot Arasan NAND driver.

    Signed-off-by: Martin Lund
    Acked-by: Siva Durga Prasad Paladugu
    Signed-off-by: Michal Simek

    Martin Lund
     

22 Nov, 2018

3 commits

  • c907464a0   mtd: rawnand: pxa3xx: fix 2kiB pages with 8b strength chips layout ... Browse Code »

    The initial layout for such NAND chips was the following:

    +----------------------------------------------------------------------------+
    | 1024 (data) | 30 (ECC) | 1024 (data) | 30 (ECC) | 32 (free OOB) | 30 (ECC) |
    +----------------------------------------------------------------------------+

    This layout has a weakness: reading empty pages trigger ECC errors
    (this is expected), but the hardware ECC engine tries to correct the
    data anyway and creates itself bitflips, hence bitflips are detected
    in erased pages while actually there are none in the NAND chip.

    Two solutions have been found at the same time. One was to enlarge the
    free OOB area to 64 bytes, changing the layout to be:

    +----------------------------------------------------------------------------+
    | 1024 (data) | 30 (ECC) | 1024 (data) | 30 (ECC) | 64 (free OOB) | 30 (ECC) |
    +----------------------------------------------------------------------------+
    ^^

    The very big drawbacks of this solution are:
    1/ It prevents booting from NAND.
    2/ The current Linux driver (marvell_nand) does not have such problem
    because it already re-reads possible empty pages in raw mode before
    checking for bitflips. Using different layouts in U-Boot and Linux
    would simply not work.

    As this driver does support raw reads now and uses it to check for
    empty pages, let's forget about this broken hack and return to the
    initial layout with only 32 free OOB bytes.

    Fixes: ac56a3b30c ("mtd: nand: pxa3xx: add support for 2KB 8-bit flash")
    Signed-off-by: Miquel Raynal
    Acked-by: Jagan Teki

    Miquel Raynal
     
  • af61ea27f   mtd: nand: pxa3xx: re-read a page in raw mode on uncorrectable error ... Browse Code »

    This only applies on BCH path.

    When an empty page is read, it triggers an uncorrectable error. While
    this is expected, the ECC engine might produce itself bitflips in the
    read data under certain layouts. To overcome this situation, always
    re-read the entire page in raw mode and check for the whole page to be
    empty.

    Also report the right number of bitflips if there are any.

    Signed-off-by: Miquel Raynal
    Acked-by: Jagan Teki

    Miquel Raynal
     
  • 6293b0361   mtd: nand: pxa3xx: add raw read support ... Browse Code »
    2

    Raw read support is added by editing a few code sections:

    ->handle_data_pio() includes the ECC bytes that are not consumed
    anymore by the ECC engine.

    ->prepare_set_command() is changed so that the ECC bytes are
    requested as part of the data I/O length.

    ->drain_fifo() shall also avoid checking the R/B pin too often
    when in raw mode.

    ->read_page_raw()/->read_oob_raw() are written from scratch.

    Signed-off-by: Miquel Raynal
    Acked-by: Jagan Teki

    Miquel Raynal
     

17 Nov, 2018

1 commit

  • 44cdfc0ec   mtd: nand: lpc32xx slc: disable DMA support in SPL builds ... Browse Code »

    Testing and analysis shows that at the moment LPC32xx NAND SLC driver
    can not get PL080 DMA backbone support in SPL build, because SPL NAND
    loaders operate with subpage (ECC step to be precisely) reads, and
    this is not supported in the NAND SLC + DMA + hardware ECC calculation
    bundle.

    The change removes a cautious build time warning and explicitly
    disables DMA flavour of the driver for SPL builds, to reduce the
    amound of #ifdef sections the code blocks are minimally reorganized.

    Signed-off-by: Vladimir Zapolskiy

    Vladimir Zapolskiy