17 Jun, 2019
1 commit
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If only FEC2 is enabled, fec_get_clk_rate will fail due to uclass_get_device
fails to get the device by using idx 1. Should use uclass_get_device_by_seq
instead, because the idx is from the udev seq which is specified by alias.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
24 May, 2019
4 commits
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Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
(cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db) -
Add support for more clocks used by iMX8 from DTB:
ref_clock, tx_2x_clock, ahb_clock
And update get clock rate interface to support multiple fec ports.Signed-off-by: Ye Li
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When the power domain driver is enabled, we need to enable clocks after power
domain on. So the clock settings can't set in board_init, needs to set them
when the device is probed. Add this weak function in driver, that SoC codes
can implement the clock settings.Reviewed-by: Peng Fan
Signed-off-by: Ye Li
(cherry picked from commit c0e4ac66196b20f363f711fb18e40b70e3be9240)
(cherry picked from commit 187ea376980be12e69c45bd6e62c7ca1559046f6) -
The MIB RAM and FIFO receive start register does not exist on
i.MX8. Accessing these register will cause SERROR in kernel.Signed-off-by: Ye Li
(cherry picked from commit 2a47ebbccb95e8482360813d6dff5288429f1248)
(cherry picked from commit fd99a9f057097a64034cd7b419fd983f487791e4)
08 Apr, 2019
2 commits
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As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
a delay of phy-reset-post-delay milliseconds will be observed after the
phy-reset-gpios has been toggled. Can be omitted thus no delay is
observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.Signed-off-by: Andrejs Cainikovs
Reviewed-by: Anatolij Gustschin
Reviewed-by: Stefano Babic
Acked-by: Joe Hershberger
Acked-by: Lukasz Majewski -
Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.Signed-off-by: Hannes Schmelzer
Tested-by: Michal Simek
Tested-by: Lukasz Majewski
15 Mar, 2019
4 commits
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Fix EC1 and EC2 read from correct offset 26, instead of 25
Signed-off-by: Pramod Kumar
Acked-by: Joe Hershberger
Reviewed-by: Prabhakar Kushwaha -
ls2088, ls1088 : minimum MC Memory size is 128 MB
lx2 : minimum MC memory size is 256 MBSigned-off-by: Meenakshi Aggarwal
Acked-by: Joe Hershberger
Reviewed-by: Prabhakar Kushwaha -
If node /board_info/ports does not exist in the DPC file,
function mc_fixup_dpc() will skip not only MAC address fixup,
but also the cache flush at the end. This may cause the other
fixup changes (e.g. ICID related ones) to be ignored by MC.Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL")
Signed-off-by: Ioana Radulescu
Acked-by: Joe Hershberger
Reviewed-by: Prabhakar Kushwaha -
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.Therefore, in fsl_rgmii_init function of SOC, we will check if the
dpmac is enabled or not? if it is (fsl_serdes_init has already enabled
the dpmac), then don't enable it.Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger
Reviewed-by: Prabhakar Kushwaha
13 Mar, 2019
1 commit
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The phy_connect_dev(...) function from phy.c does all the handling
(inclusive catching fixed-link).So we drop here the single steps and call just phy_connect_dev(...).
Signed-off-by: Hannes Schmelzer
Acked-by: Joe Hershberger
27 Feb, 2019
2 commits
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Fix MID bit field check to correctly identify all GEM hardwares.
The check is updated as per macb driver in Linux location:
/drivers/net/ethernet/cadence/macb_main.c:259Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
Acked-by: Joe Hershberger -
Don't fail in macb_enable_clk() if clk_enable() returns
-ENOSYS because we get -ENOSYS for fixed-rate clocks.Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
18 Feb, 2019
2 commits
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Enable the socfpga specific designware ethernet driver by default for
socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a
MACH_SOCFPGA config.This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.Signed-off-by: Simon Goldschmidt
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This driver was written for Arria10, but it applies to Gen5, too.
The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the
syscon bits are encoded in the same register, thus an offset is needed.This offset is already read from the devicetree, but for Arria10 it is
always 0, which is probably why it has been ignored. By using this
offset when writing the phy mode into the syscon regiter, we can use
this driver to set the phy mode for both of the MACs on Gen5.Since the PHY mode bits in sysmgr are the same even for Stratix10,
let's drop the detection of the sub-mach by checking compatible
version and just use the same code for all FPGAs.To work correctly, this driver depends on SYSCON and REGMAP, so select
those via Kconfig when it is enabeld.Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift
offset is required).Signed-off-by: Simon Goldschmidt
15 Feb, 2019
2 commits
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phy_reset should be called before autoneg is setup
The only boards using MV88E61XX_SWITCH are:
- alliedtelesis/SBx81LIFKW
- alliedtelesis/SBx81LIFXCAT
- gateworks/gw_ventanaCc: Chris Packham
Signed-off-by: Tim Harvey
Reviewed-by: Chris Packham -
When DM_REGULATOR is enabled, the driver attempts to call
regulator_autoset() which expects the regulators to be on at boot
and/or always on and fails if they are not true.
For a more generic approach, this patch just calls
regulator_set_enable() which shouldn't have such restrictions.Fixes: ad8c43cbcafb ("net: dm: fec: Support the phy-supply
binding")Signed-off-by: Adam Ford
Tested-by: Martin Fuzzey
Acked-by: Joe Hershberger
01 Feb, 2019
6 commits
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Add network driver for Microsemi Ethernet switch, it is
present on Luton SoCs.Signed-off-by: Horatiu Vultur
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Remove unused variables in the struct ocelot_private and make
miim variable static.Signed-off-by: Horatiu Vultur
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Move the function mac_table_add into a different file,
so it can be reused.Signed-off-by: Horatiu Vultur
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This functions can be reused by other MSCC SoCs therefore,
make them more generic and move them in separate files.Signed-off-by: Horatiu Vultur
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Move miim functions that can be shared in a different file inside
mscc_eswitch.Signed-off-by: Horatiu Vultur
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Move file ocelot_switch to mscc_eswitch to prepare to add
new net drivers for other MSCC SoCs.Signed-off-by: Horatiu Vultur
28 Jan, 2019
1 commit
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Currently if we have more than one phy on the MDIO bus, we do not have a
good mechanism for determining which should be used at runtime. Enable the
FEC driver to determine the address for the PHY from the device tree.Signed-off-by: Martyn Welch
Reviewed-by: Lukasz Majewski
25 Jan, 2019
15 commits
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Print information about Aquantia system interface and firmware loaded
on the phy.Signed-off-by: Valentin Catalin Neacsu
Acked-by: Joe Hershberger -
If System Interface protocol is USXGMII then enable USXGMII autoneg
Signed-off-by: Valentin Catalin Neacsu
Acked-by: Joe Hershberger -
No mainline board enables CONFIG_MCAST_TFTP and there have been
compilation issues with the code for some time. Additionally, it has a
potential buffer underrun issue (reported as a side note in
CVE-2018-18439).Remove the multicast TFTP code but keep the driver API for the future
addition of IPv6.Cc: Simon Goldschmidt
Signed-off-by: Chris Packham
Acked-by: Joe Hershberger -
ether_crc was added to the core net code in commit 53a5c424bf86
("multicast tftp: RFC2090") so that other drivers could use it. However
the only current user of it is tsec.c so move it there.Signed-off-by: Chris Packham
Acked-by: Joe Hershberger -
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
Standard Registers)Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.Signed-off-by: Carlo Caione
Acked-by: Joe Hershberger -
Some architectures (MIPS) needs mapping to access IOMEM.
Fix that.Fixes: f1dcc19b213d ("net: macb: Convert to driver model")
Signed-off-by: Ramon Fried
Acked-by: Joe Hershberger -
This patch add GPIO configuration support in mvneta driver.
Driver will handle PHY reset. GPIO pins should be set in device tree.Ported from mvpp2x
[https://patchwork.ozlabs.org/patch/799654/]Initial discussion to port the changes into mvneta
[https://patchwork.ozlabs.org/patch/1005765/]Signed-off-by: Aditya Prayoga
Tested-by: Dennis Gilmore
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
Some existing device trees don't specify a phy-mode so fallback to GMII
when a phy-mode is not provided.Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.Fix the check by using the bit width instead of hardcoded value(s).
Signed-off-by: Andreas Pretzsch
Acked-by: Joe Hershberger -
Current code forces all ports on a given Ethernet device to use the same
mdio device. In practice different ports might be wired to separate mdio
devices. Move the mdio device from the container struct mvpp2 to the per
port struct mvpp2_port.Cc: Ken Ma
Cc: Stefan Chulski
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
Current mdio base lookup code relies on a 'reg' property at the upper CP
node. There is no 'reg' property there in current DT files of Armada
CP110. Use ofnode_get_addr() instead since it provides proper DT address
translation.Cc: Ken Ma
Cc: Stefan Chulski
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Acked-by: Joe Hershberger -
Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.Fix the padding code to zero out the padded bytes at the end.
Tested on socfpga gen5.
Signed-off-by: Simon Goldschmidt
Acked-by: Joe Hershberger -
The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.Fix this by correctly clearing the size mask before setting the new
length.Tested on socfpga gen5.
Signed-off-by: Simon Goldschmidt
Acked-by: Joe Hershberger
Reviewed-by: Philipp Tomsich -
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger
