28 Apr, 2017

13 commits


27 Apr, 2017

2 commits


26 Apr, 2017

2 commits


25 Apr, 2017

18 commits


24 Apr, 2017

2 commits

  • Since commit ce412b7, RGMII TX clock internal delay is not enabled
    for AR8033 unconditionally. On LS1021ATWR board, the third port
    eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to
    be enabled.

    This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX
    clock internal delay for AR8033 on the third port.

    Signed-off-by: Alison Wang
    Reviewed-by: York Sun

    Alison Wang
     
  • Currently $fdtfile is constructed from CONFIG_DEFAULT_TREE, containing
    the filename. However on arm64 that file is located in an allwinner
    subdirectory.

    To avoid the need for users/distros symlinking the .dtb files, prepend
    the vendor directory for ARM64.

    This aligns Pine64 with other boards such as Raspberry Pi 3.

    Signed-off-by: Andreas Färber
    Reviewed-by: Alexander Graf
    Reviewed-by: Jagan Teki

    Andreas Färber
     

21 Apr, 2017

3 commits

  • Before this patch, CONFIG_SYS_BOOTPARAMS_LEN was the same size as
    CONFIG_SYS_MALLOC_LEN. So, if malloc() had previously been called, and
    initr_malloc_bootparams() was called, it would fail with an out-of-
    memory error. This patch fixes this issue by expanding the malloc pool
    to 256KB.

    Signed-off-by: Kyle Edwards
    Cc: Daniel Schwierzeck

    Kyle Edwards
     
  • This fixes an issue with the saveenv command causing U-Boot to no
    longer work on the QEMU Mips pseudoboard. Because the offset of the
    environment was being determined by CONFIG_SYS_MONITOR_LEN, and this
    value was less than the actual size of U-Boot, saveenv was overwriting
    parts of the U-Boot code. Because CONFIG_SYS_MONITOR_LEN is no longer
    used on MIPS, this patch removes it and places the environment at the
    end of the pseudoboard's 4MB flash.

    Signed-off-by: Kyle Edwards
    Cc: Daniel Schwierzeck

    Kyle Edwards
     
  • Lichee Pi Zero is a development board with a V3s SoC, which features
    64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
    soldered in production batch), a 40-pin RGB LCD connector and some extra
    pins available as 2.54mm pins or stamp holes.

    Add support for it.

    Signed-off-by: Icenowy Zheng
    Signed-off-by: Maxime Ripard

    Icenowy Zheng